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freescale.com microcontrollers m68hc05 mc68hc05b4 mc68hc705b5 mc68hc05b5 mc68HC05B6 mc68hc05b8 mc68hc05b16 mc68hc705b16 mc68hc705b16n mc68hc05b32 mc68hc705b32 technical data mc68HC05B6/d rev. 4.1 08/2005

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 introduction modes of operation and pin descriptions memory and registers input/output ports programmable timer serial communications interface pulse length d/a converters analog to digital converter resets and interrupts cpu core and in struction set electrical specifications mechanical data ordering information appendices high speed operation tpg 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 introduction modes of operation and pin descriptions memory and registers input/output ports programmable timer serial communications interface pulse length d/a converters analog to digi tal converter resets and interrupts cpu core and instruction set electrical specifications mechanical data ordering information appendices high speed operation tpg 3
customer feedback questionnaire (mc68HC05B6/d rev. 4) motorola wishes to continue to improve the quality of its documentation. we would welcome your feedback on the publication you have just received. having used the document, please comple te this card (or a photocopy of it, if you prefer). 1. how would you rate the quality of the document? check one box in each category. excellent poor excellent poor organization ???? ta bl e s ???? readability ???? table of contents ???? understandability ???? index ???? accuracy ???? page size/binding ???? illustrations ???? overall impression ???? comments: 2. what is your intended use for this document? if more than one option applies, please rank them (1, 2, 3). selection of device for new application ? other ? please specify: system design ? training purposes ? 3. how well does this manual enable you to perform the task(s) outlined in question 2? completely not at all comments: ???? 4. how easy is it to find the information you are looking for? easy difficult comments: ???? 5. is the level of technical detail in the following sections sufficient to allow you to understand how the device functions? too little detail too much detail comments: 6. have you found any errors? if so, please comment: 7. from your point of view, is anything missin g from the document? if so, please say what: ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ????? ? cut along this line to remove ? section 1 introduction section 2 modes of operat ion and pin descriptions section 3 memory and registers section 4 input/output ports section 5 programmable timer section 6 serial communications interface section 7 pulse length d/a converters section 8 analog to digital converter section 9 resets and interrupts section 10 cpu core and instruction set section 11 electrical specifications section 12 mechanical data section 13 ordering information section 14 appendices section 15 high speed operation tpg 4
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freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the applicatio n or use of any product or circuit, and sp ecifically disclaims any and all liability , including without limitation consequential or incident al damages. ?typical? parameters which may be provided in freescale data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each cust omer application by customer?s technical experts. freescale does not convey any licens e under its patent rights nor the rights of others. freescale products are not designed, intended, or authorized for use as components in systems intended for surg ical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale product could create a situation wh ere personal injury or death may occur. should buyer purc hase or use freescale products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associat ed with such unintended or unauthorized use, even if such claim alleges that freescale was negligent regarding the design or manufacture of the part. freescale, inc. is an equal opportunity/affirmative action employer. all products are sold on freescale?s terms & conditions of supply. in ordering a product covered by this document the customer agrees to be bound by those terms & conditions and nothing contained in this document constitutes or forms part of a contract (with the exception of the contents of this notice ). a copy of freescale?s terms & conditions of supply is availa ble on request. the customer should ensure that it has the most up to date version of the document by contacting its local freescale office. this document supersedes any earlier documentation relating to the products referred to herein. the information contained in this document is current at the date of publication. it may subsequently be updated, revised or withdrawn. ? freescale ltd., 2005 all trade marks recognized. this document contains information on new products. specifications and information herein are subject to change without notice. mc68HC05B6 high-density complementary metal oxide semiconductor (hcmos) microcomputer unit tpg 6
conventions where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this manual. register and bit mnemonics are defined in the paragraphs describing them. an overbar is used to designate an active-low signal, eg: reset . unless otherwise stated, shaded cells in a register diagram indicate that the bit is either unused or reserved; ?u? is used to indicate an undefined state (on reset). unless otherwise stated, pins labelled ?nu? should be tied to v ss in an electrically noisy environment. pins labelled ?nc? can be left floating, since they are not bonded to any part of the device. tpg 6
mc68HC05B6 rev. 4.1 freescale i table of contents paragraph number page number title table of contents 1 introduction 1.1 features.............................................................................................................1?2 1.2 mask options for the mc68HC05B6 ..................................................................1?3 2 modes of operation and pin descriptions 2.1 modes of operation ............................................................................................2?1 2.1.1 single chip mode .........................................................................................2?1 2.2 serial ram loader .............................................................................................2?2 2.3 ?jump to any address?........................................................................................2?4 2.4 low power modes..............................................................................................2?6 2.4.1 stop ...........................................................................................................2?6 2.4.2 wait ............................................................................................................2?8 2.4.2.1 power consumption during wait mode .................................................2?8 2.4.3 slow mode.................................................................................................2?9 2.4.3.1 miscellaneous register.. .............. .............. .............. ........... ........... .........2?9 2.5 pin descriptions ...... .............. .............. .............. .............. .............. ........... .......2?10 2.5.1 vdd and vss ....... .............. .............. .............. .............. ........... ........... .......2?10 2.5.2 irq ............... .............. .............. .............. .............. .............. .............. .........2?10 2.5.3 reset ............ .............. .............. .............. .............. .............. .............. .......2?10 2.5.4 tcap1 .......... .............. .............. .............. .............. .............. .............. .........2?10 2.5.5 tcap2 .......... .............. .............. .............. .............. .............. .............. .........2?11 2.5.6 tcmp1.......... .............. .............. .............. .............. .............. .............. .........2?11 2.5.7 tcmp2.......... .............. .............. .............. .............. .............. .............. .........2?11 2.5.8 osc1, osc2 ........ .............. .............. .............. .............. ........... ........... .......2?11 2.5.8.1 crystal .......... .............. .............. .............. .............. .............. ........... .......2?11 2.5.8.2 ceramic resonator...... .............. .............. .............. .............. ........... .......2?11 2.5.8.3 external clock .......... .............. .............. .............. .............. .............. .......2?12 2.5.9 rdi (receive data in)... ............. .............. .............. .............. .............. .........2?13 2.5.10 tdo (transmit data out) ............. .............. .............. .............. .............. .......2?13 2.5.11 sclk.......... .............. .............. .............. .............. ........... ........... ........... .......2?13 2.5.12 plma ............ .............. .............. .............. .............. .............. .............. .........2?13
freescale ii mc68HC05B6 rev. 4.1 table of contents paragraph number page number table of contents 2.5.13 plmb ......................................................................................................... 2?13 2.5.14 vpp1.............. .............. .............. .............. .............. .............. .............. ........ 2?13 2.5.15 vrh ........................................................................................................... 2?13 2.5.16 vrl............................................................................................................ 2?13 2.5.17 pa0 ? pa7/pb0 ? pb7/pc0 ? pc7 ............................................................ 2?13 2.5.18 pd0/an0?pd7/an7................................................................................... 2?13 3 memory and registers 3.1 registers ........................................................................................................... 3?1 3.2 ram .................................................................................................................. 3?1 3.3 rom .................................................................................................................. 3?1 3.4 self-check rom ................................................................................................ 3?2 3.5 eeprom ............. .............. .............. .............. .............. ........... ........... ............ .... 3?3 3.5.1 eeprom control register .. .............. .............. .............. .............. .............. .... 3?3 3.5.2 eeprom read operation ..... .............. .............. .............. .............. ............ .... 3?5 3.5.3 eeprom erase operation ... .............. .............. .............. .............. ............ .... 3?5 3.5.4 eeprom programming oper ation ........ .............. .............. ........... ............ .... 3?6 3.5.5 options register (optr) .............................................................................. 3?6 3.6 eeprom during stop mode .. ............. .............. .............. .............. .............. .... 3?7 3.7 eeprom during wait mode .. .............. .............. .............. .............. .............. .... 3?7 3.8 miscellaneous register...................................................................................... 3?9 4 input/output ports 4.1 input/output programming ................................................................................. 4?1 4.2 ports a and b .................................................................................................... 4?2 4.3 port c ................................................................................................................ 4?3 4.4 port d ................................................................................................................ 4?3 4.5 port registers ..................................................................................................... 4?4 4.5.1 port data registers a and b (porta and portb) ...................................... 4?4 4.5.2 port data register c (portc)...................................................................... 4?4 4.5.3 port data register d (portd)...................................................................... 4?5 4.5.3.1 a/d status/control register...................................................................... 4?5 4.5.4 data direction registers (ddra, ddrb and ddrc)......... ........... ............ .... 4?5 4.6 other port considerations ........................ .......................................................... 4?6
mc68HC05B6 rev. 4.1 freescale iii table of contents paragraph number page number table of contents 5 programmable timer 5.1 counter..............................................................................................................5?1 5.1.1 counter register and alternate counte r register ...........................................5?3 5.2 timer control and status ....................................................................................5?4 5.2.1 timer control register (tcr) ........................................................................5?4 5.2.2 timer status register (tsr)..........................................................................5?6 5.3 input capture......................................................................................................5?7 5.3.1 input capture register 1 (icr1) ....................................................................5?7 5.3.2 input capture register 2 (icr2) ....................................................................5?8 5.4 output compare .................................................................................................5?9 5.4.1 output compare register 1 (ocr1)..............................................................5?9 5.4.2 output compare register 2 (ocr2)...... .............. ........... ........... ........... .......5?10 5.4.3 software force compare ... .............. .............. .............. .............. ........... .......5?11 5.5 pulse length modulation (plm ) ............. .............. .............. ........... ........... .......5?11 5.5.1 pulse length modulation registers a and b (plma/plmb) ... .............. .......5?11 5.6 timer during stop mode.. ............. .............. .............. .............. .............. .........5?12 5.7 timer during wait mode.. .............. .............. .............. .............. .............. .........5?12 5.8 timer state diagrams ........ .............. .............. .............. .............. .............. .........5?12 6 serial communications interface 6.1 sci two-wire system features ............................................................................6?1 6.2 sci receiver features .........................................................................................6?3 6.3 sci transmitter features.....................................................................................6?3 6.4 functional description....... .............. .............. .............. .............. .............. ...........6?3 6.5 data format ........................................................................................................6?5 6.6 receiver wake-up operation ..............................................................................6?5 6.6.1 idle line wake-up ..........................................................................................6?6 6.6.2 address mark wake-up ................................................................................6?6 6.7 receive data in (rdi) ........................................................................................6?6 6.8 start bit detection...............................................................................................6?6 6.9 transmit data out (tdo) ....................................................................................6?8 6.10 sci synchronous transmission .................. ........................................................6?9 6.11 sci registers ......... .............. .............. .............. .............. .............. .............. .......6?10 6.11.1 serial communications data register (scdr) ............ .............. ........... .......6?10 6.11.2 serial communications control regist er 1 (sccr1) ............ .............. .........6?10 6.11.3 serial communications control regist er 2 (sccr2) ............ .............. .........6?14 6.11.4 serial communications status register (scsr)....... .............. .............. .......6?16 6.11.5 baud rate register (b aud) .......... .............. .............. .............. .............. .......6?18 6.12 baud rate selection ........... .............. .............. .............. .............. .............. .........6?19 6.13 sci during stop mode ...... .............. .............. .............. .............. .............. .......6?21 6.14 sci during wait mode....... .............. .............. .............. .............. .............. .......6?21
freescale iv mc68HC05B6 rev. 4.1 table of contents paragraph number page number table of contents 7 pulse length d/a converters 7.1 miscellaneous register............................. .......................................................... 7?3 7.2 plm clock selection................................. .......................................................... 7?4 7.3 plm during stop mode ................................................................................... 7?4 7.4 plm during wait mode .................................................................................... 7?4 8 analog to digital converter 8.1 a/d converter operation..................................................................................... 8?1 8.2 a/d registers...................................................................................................... 8?3 8.2.1 port d data register (portd)...................................................................... 8?3 8.2.2 a/d result data register (addata) ........ ....................................................... 8?3 8.2.3 a/d status/control register (adstat).... ....................................................... 8?4 8.3 a/d converter during stop mode..................................................................... 8?6 8.4 a/d converter during wait mode...................................................................... 8?6 8.5 port d analog input............................................................................................ 8?6 9 resets and interrupts 9.1 resets ............................................................................................................... 9?1 9.1.1 power-on reset............................................................................................. 9?2 9.1.2 miscellaneous register ...... .............. .............. .............. .............. .............. .... 9?2 9.1.3 reset pin ................................................................................................... 9?3 9.1.4 computer operating properly (cop) watc hdog reset ............. .............. ....... 9?3 9.1.4.1 cop watchdog during stop mode ...... .............. .............. .............. ....... 9?4 9.1.4.2 cop watchdog during wait mode .... .............. ........... ........... ............ .... 9?4 9.1.5 functions affected by reset................ .......................................................... 9?5 9.2 interrupts ........................................................................................................... 9?6 9.2.1 interrupt priorities......................................................................................... 9?6 9.2.2 nonmaskable software interrupt (swi) ........................................................ 9?6 9.2.3 maskable hardware interrupts .............. ....................................................... 9?7 9.2.3.1 external interrupt (irq ).......................................................................... 9?7 9.2.3.2 miscellaneous register .......................................................................... 9?9 9.2.3.3 timer interrupts .................................................................................... 9?10 9.2.3.4 serial communications interface (sci ) interrupts................................. 9?10 9.2.4 hardware controlled interrupt sequence.. .............. .............. .............. ........ 9?11
mc68HC05B6 rev. 4.1 freescale v table of contents paragraph number page number table of contents 10 cpu core and instruction set 10.1 registers .............. .............. .............. .............. .............. .............. .............. .......10?1 10.1.1 accumulator (a) ............ .............. .............. .............. .............. .............. .......10?2 10.1.2 index register (x)......... .............. .............. .............. .............. .............. .........10?2 10.1.3 program counter (pc) ... .............. .............. .............. .............. .............. .......10?2 10.1.4 stack pointer (sp) ....... .............. .............. .............. .............. .............. .........10?2 10.1.5 condition code register (ccr).......... .............. .............. ........... ........... .......10?2 10.2 instruction set ................ .............. .............. .............. ........... ........... ........... .......10?3 10.2.1 register/memory instruct ions .............. .............. ........... ........... ........... .......10?4 10.2.2 branch instructions ..... .............. .............. .............. .............. .............. .........10?4 10.2.3 bit manipulation instruct ions .......... .............. .............. .............. ........... .......10?4 10.2.4 read/modify/write instru ctions ............. .............. ........... ........... ........... .......10?4 10.2.5 control instructions ..... .............. .............. .............. .............. .............. .........10?4 10.2.6 tables................. .............. .............. .............. .............. .............. ........... .......10?4 10.3 addressing modes .............. .............. .............. .............. .............. .............. .....10?11 10.3.1 inherent.............. .............. .............. .............. .............. .............. ........... .....10?11 10.3.2 immediate .......... .............. .............. .............. .............. .............. ........... .....10?11 10.3.3 direct.................. .............. .............. .............. .............. .............. ........... .....10?11 10.3.4 extended............ .............. .............. .............. .............. .............. ........... .....10?12 10.3.5 indexed, no offset........ .............. .............. .............. .............. .............. .......10?12 10.3.6 indexed, 8-bit offset..... .............. .............. .............. .............. .............. .......10?12 10.3.7 indexed, 16-bit offset... .............. .............. .............. .............. .............. .......10?12 10.3.8 relative .............. .............. .............. .............. .............. .............. ........... .....10?13 10.3.9 bit set/clear ........ .............. .............. .............. .............. .............. ........... .....10?13 10.3.10 bit test and branch ...... .............. .............. .............. .............. .............. .......10?13 11 electrical specifications 11.1 absolute maximum ratings . .............. .............. .............. .............. .............. .......11?1 11.2 dc electrical characteristic s ............. .............. .............. .............. .............. .......11?2 11.2.1 i dd trends for 5v operation .... .............. .............. ........... ........... ........... .......11?3 11.2.2 i dd trends for 3.3v operation . .............. .............. ........... ........... ........... .......11?6 11.3 a/d converter characterist ics............ .............. .............. .............. .............. .......11?8 11.4 control timing ....... .............. .............. .............. .............. .............. .............. .....11?10 12 mechanical data 12.1 mc68hc05b family pin configurations ...... .............. ........... ........... ........... .......12?1 12.1.1 52-pin plastic leaded chip carrier (p lcc) .......... ........... ........... ........... .......12?1 12.1.2 64-pin quad flat pack (qfp) .............. .............. .............. ........... ........... .......12?2
freescale vi mc68HC05B6 rev. 4.1 table of contents paragraph number page number table of contents 12.1.3 56-pin shrink dual in line package (sdip).................................................. 12?3 12.2 mc68HC05B6 mechanical dimensions ........................................................... 12?4 12.2.1 52-pin plastic leaded chip carrier (pl cc) .................................................. 12?4 12.2.2 64-pin quad flat pack (qfp )............... .............. .............. ............ ........... ..... 12?5 12.2.3 56-pin shrink dual in line package (sdip).................................................. 12?6 13 ordering information 13.1 eproms ......................................................................................................... 13?2 13.2 verification media ............................................................................................ 13?2 13.3 rom verification units (rvu)........................................................................... 13?2 a mc68hc05b4 a.1 features ........................................................................................................... a?1 a.2 self-check mode............................................................................................... a?5 b mc68hc05b8 b.1 features ........................................................................................................... b?1 c mc68hc705b5 c.1 features ........................................................................................................... c?1 c.2 eprom ............................................................................................................ c?5 c.2.1 eprom programming operation................................................................. c?5 c.3 eprom registers.............................................................................................. c?6 c.3.1 eprom control register.............................................................................. c?6 c.4 options register (optr)................................................................................... c?7 c.5 bootstrap mode ................................................................................................ c?8 c.5.1 erased eprom verification ...................................................................... c?11 c.5.2 eprom parallel bootstrap load ................................................................ c?11 c.5.3 eprom (ram) serial bootstrap load and execute ................................... c?13 c.5.4 ram parallel bootstrap load and execute ................................................. c?14 c.5.5 bootstrap loader timing diagrams ...... ....................................................... c?17 c.6 dc electrical characteristics ........................................................................... c?19 c.7 control timing ................................................................................................. c?19
mc68HC05B6 rev. 4.1 freescale vii table of contents paragraph number page number table of contents d mc68hc05b16 d.1 features............................................................................................................ d?1 d.2 self-check routines ........................................................................................... d?2 d.3 external clock ................................................................................................... d?4 e mc68hc705b16 e.1 features............................................................................................................ e?2 e.2 external clock ................................................................................................... e?5 e.3 eprom............................................................................................................. e?5 e.3.1 eprom read operation............................................................................... e?5 e.3.2 eprom program operation......................................................................... e?5 e.3.3 eprom/eeprom/eclk control register . .............. .............. .............. ........ e?6 e.3.4 mask option register.................................................................................... e?8 e.3.5 eeprom options register (optr) ......... .............. ........... ........... ........... ..... e?9 e.4 bootstrap mode .............................................................................................. e?10 e.4.1 erased eprom verification ...................................................................... e?13 e.4.2 eprom/eeprom parallel bootstrap........ .............. .............. .............. ...... e?13 e.4.3 eeprom/eprom/ram serial bootstrap.. .............. .............. .............. ...... e?16 e.4.4 ram parallel bootstrap ............................................................................. e?19 e.4.4.1 jump to start of ram ($0050) ............................................................. e?20 e.5 absolute maximum ratings ............................................................................. e?21 e.6 dc electrical characteristics ........................................................................... e?22 e.7 a/d converter characteristics.......................................................................... e?24 e.8 control timing ................................................................................................. e?26 e.9 eprom electrical characteristics ................................................................... e?28 f mc68hc705b16n f.1 features............................................................................................................ f?2 f.2 external clock ................................................................................................... f?5 f.3 reset pin........................................................................................................ f?5 f.4 eprom............................................................................................................. f?5 f.4.1 eprom read operation............................................................................... f?5 f.4.2 eprom program operation......................................................................... f?6 f.4.3 eprom/eeprom/eclk control register . .............. .............. .............. ........ f?6 f.4.4 mask option register.................................................................................... f?8 f.4.5 eeprom options register (optr) ......... .............. ........... ........... ........... ..... f?9 f.5 bootstrap mode .............................................................................................. f?10 f.5.1 erased eprom verification ...................................................................... f?13
freescale viii mc68HC05B6 rev. 4.1 table of contents paragraph number page number table of contents f.5.2 eprom/eeprom parallel bootstrap............. .............. .............. ........... .....f?13 f.5.3 serial ram loader......................................................................................f?16 f.5.3.1 jump to start of ram ($0051) ......... .............. ........... ............ ................f?16 f.6 absolute maximum ratings ..............................................................................f?19 f.7 dc electrical characteristics ............................................................................f?20 f.8 a/d converter characteristics ..........................................................................f?22 f.9 control timing ..................................................................................................f?24 f.10 eprom electrical characteristics ....................................................................f?26 g mc68hc05b32 g.1 features ........................................................................................................... g?1 g.2 external clock ................................................................................................... g?2 h mc68hc705b32 h.1 features ........................................................................................................... h?3 h.2 external clock ................................................................................................... h?7 h.3 reset pin........................................................................................................ h?7 h.4 eprom ............................................................................................................ h?7 h.4.1 eprom read operation............................................................................... h?8 h.4.2 eprom program operation ........................................................................ h?8 h.4.3 eprom/eeprom cont rol register .......... .............. .............. .............. ......... h?8 h.4.4 mask option register ................................................................................. h?11 h.4.5 options register (optr) ........................................................................... h?12 h.5 bootstrap mode .............................................................................................. h?13 h.5.1 erased eprom verification ...................................................................... h?16 h.5.2 eprom/eeprom parallel bootstrap............. .............. .............. ........... .... h?16 h.5.3 serial ram loader..................................................................................... h?19 h.5.3.1 jump to start of ram ($0051) ......... .............. ........... ............ ........... .... h?19 h.6 absolute maximum ratings ............................................................................. h?22 h.7 dc electrical characteristics ........................................................................... h?23 h.8 a/d converter characteristics ......................................................................... h?25 h.9 control timing ................................................................................................. h?27 h.10 eprom electrical characteristics ................................................................... h?29 i high speed operation i.1 dc electrical characteristics ............................................................................... i?2 i.2 a/d converter characteristics ............................................................................. i?3 i.3 control timing for 5v operatio n.............. .............. .............. .............. .............. .....i?4
mc68HC05B6 rev. 4.1 freescale ix list of figures figure number page number title list of figures 1-1 mc68HC05B6 block diagram ............................................................................. 1?3 2-1 mc68HC05B6 ?load program in ram and execute? schematic diagram ............ 2?3 2-2 mc68HC05B6 ?jump to any address? schematic diagram .................................. 2?5 2-3 stop and wait flowcharts................................................................................ 2?7 2-4 slow mode divider block diagram ................ .............. .............. ........... ........... ..... 2?9 2-5 oscillator connections ....... .............. .............. .............. .............. .............. ......... 2?12 3-1 memory map of the mc68HC05B6 ............... ..................................................... 3?2 4-1 standard i/o port structure................................................................................. 4?2 4-2 eclk timing diagram.......................................................................................... 4?3 4-3 port logic levels................................................................................................... 4?6 5-1 16-bit programmable timer block diagram ... ....................................................... 5?2 5-2 timer state timing diagram for reset ................................................................. 5?13 5-3 timer state timing diagram for input capture .................................................... 5?13 5-4 timer state timing diagram for output compare ................................................ 5?14 5-5 timer state timing diagram for timer overflow................................................... 5?14 6-1 serial communications interface block diag ram ................................................. 6?2 6-2 sci rate generator division ....................... .......................................................... 6?4 6-3 data format......................................................................................................... 6?5 6-4 sci examples of start bit sampling techni que .................................................... 6?7 6-5 sci sampling technique used on all bits...... ....................................................... 6?7 6-6 artificial start following a framing error .. ............................................................. 6?8 6-7 sci start bit following a break............................................................................. 6?8 6-8 sci example of synchronous and asynch ronous transmission .......................... 6?9 6-9 sci data clock timing diagram (m=0) ............................................................... 6?12 6-10 sci data clock timing diagram (m=1) ............................................................... 6?13 7-1 plm system block diagram... .............. .............. .............. .............. .............. ........ 7?1 7-2 plm output waveform examples ........................................................................ 7?2 7-3 plm clock selection............................................................................................ 7?4 8-1 a/d converter block diagram .............................................................................. 8?2 8-2 electrical model of an a/d input pin ......... .......................................................... 8?6 9-1 reset timing diagram.......................................................................................... 9?1 9-2 watchdog system block diagra m .............. .............. .............. .............. ........... ..... 9?3 9-3 interrupt flow chart.............................................................................................. 9?8
freescale x mc68HC05B6 rev. 4.1 list of figures figure number page number title 10-1 programming model ............... .............. .............. .............. .............. ........... ....... 10?1 10-2 stacking order .......... .............. .............. .............. .............. .............. ........... ....... 10?1 11-1 run i dd vs internal operating frequency (4.5v, 5.5v) ........ ............ ........... ....... 11?3 11-2 run i dd (sm = 1) vs internal operating fre quency (4.5v, 5.5v) .. .............. ....... 11?3 11-3 wait i dd vs internal operating frequency (4.5v, 5.5v)........ ............ ........... ....... 11?3 11-4 wait i dd (sm = 1) vs internal operating frequen cy (4.5v, 5.5v).. .............. ....... 11?4 11-5 increase in i dd vs frequency for a/d, sci system s active, vdd = 5.5v........... 11?4 11-6 i dd vs mode vs internal operating frequency, v dd = 5.5v ............. ........... ....... 11?4 11-7 run i dd vs internal operating frequency (3 v, 3.6v)........... ............ ........... ....... 11?6 11-8 run i dd (sm = 1) vs internal operating fre quency (3v,3.6v) ...... .............. ....... 11?6 11-9 wait i dd vs internal operating frequency (3v, 3.6v)........... ............ ........... ....... 11?6 11-10 wait i dd (sm = 1) vs internal operating frequen cy (3v, 3.6v)..... .............. ....... 11?7 11-11 increase in i dd vs frequency for a/d, sci systems active, v dd = 3.6v............ 11?7 11-12 i dd vs mode vs internal operating frequency, v dd = 3.6v ............. ........... ....... 11?7 11-13 timer relationship.. .............. .............. .............. .............. .............. .............. ..... 11?12 12-1 52-pin plcc pinout for the mc68HC05B6... .............. .............. .............. .......... 12?1 12-2 64-pin qfp pinout for the mc68HC05B6.. .............. ........... ............ ........... ....... 12?2 12-3 56-pin sdip pinout for the mc68HC05B6. .............. ........... ............ ........... ....... 12?3 12-4 52-pin plcc mechanical dimensions .......... .............. .............. .............. .......... 12?4 12-5 64-pin qfp mechanical dimensions.......... .............. ........... ............ ........... ....... 12?5 12-6 56-pin sdip mechanical dimensions......... .............. ........... ............ ........... ....... 12?6 a-1 mc68hc05b4 block diagram .............................................................................a?2 a-2 memory map of the mc68hc05b4 ....................................................................a?3 a-3 mc68hc05b4 self-check schematic diagra m ....................................................a?7 b-1 mc68hc05b8 block diagram .............................................................................b?2 b-2 memory map of the mc68hc05b8 ....................................................................b?3 c-1 mc68hc705b5 block diagram ...........................................................................c?2 c-2 memory map of the mc68hc705b5 ..................................................................c?3 c-3 modes of operation flow chart (1 of 2)................................................................c?9 c-4 modes of operation flow chart (2 of 2)..............................................................c?10 c-5 timing diagram with handshake.......................................................................c?11 c-6 eprom(ram) parallel bootstrap schemati c diagram ......................................c?12 c-7 eprom (ram) serial bootstrap schematic diagram ........................................c?15 c-8 ram parallel bootstrap schematic diagram......................................................c?16 c-9 eprom parallel bootstrap loader timing diagram ............................................c?17 c-10 ram parallel loader timing diagram ................................................................c?18 d-1 mc68hc05b16 block diagram ...........................................................................d?3 d-2 oscillator connections ......... .............. .............. .............. .............. .............. .........d?4 d-3 memory map of the mc68hc05b16 ..................................................................d?5 e-1 mc68hc705b16 block diagram .........................................................................e?2 e-2 memory map of the mc68hc705b16 ................................................................e?3 e-3 modes of operation flow chart (1 of 2)..............................................................e?11
mc68HC05B6 rev. 4.1 freescale xi list of figures figure number page number title e-4 modes of operation flow chart (2 of 2) ...... .............. .............. ........... ........... ......e?12 e-5 timing diagram with handshake .................. .............. ........... ........... ........... ......e?14 e-6 parallel eprom loader timing diagram ....... .............. ........... ........... ........... ......e?14 e-7 eprom parallel bootstrap schematic diagram.................................................e?15 e-8 ram/eprom/eeprom serial bootstrap sc hematic diagram ...... .............. ......e?17 e-9 parallel ram loader timing diagram .................................................................e?19 e-10 ram parallel bootstrap schematic diagram ......................................................e?20 e-11 timer relationship .............................................................................................e?28 f-1 mc68hc705b16n block diagram.......................................................................f?2 f-2 memory map of the mc68hc705b16n......... .....................................................f?3 f-3 modes of operation flow chart (1 of 2) ...... .............. .............. ........... ........... ......f?11 f-4 modes of operation flow chart (2 of 2) ...... .............. .............. ........... ........... ......f?12 f-5 timing diagram with handshak e ............... .............. .............. ........... ........... ......f?14 f-6 parallel eprom loader timing diagram ....... .............. ........... ........... ........... ......f?14 f-7 eprom parallel bootstrap schematic diagram.................................................f?15 f-8 ram load and execute schematic diagram . .............. ........... ........... ........... ......f?17 f-9 parallel ram loader timing diagram .................................................................f?18 f-10 timer relationship .............................................................................................f?26 g-1 mc68hc05b32 block diagram .......................................................................... g?2 g-2 memory map of the mc68hc05b32 ................................................................. g?3 h-1 mc68hc705b32 block diagram ........................................................................ h?4 h-2 memory map of the mc68hc705b32 ........... .................................................... h?5 h-3 modes of operation flow chart (1 of 2) ...... .............. .............. ........... ........... ..... h?14 h-4 modes of operation flow chart (2 of 2) ...... .............. .............. ........... ........... ..... h?15 h-5 timing diagram with handshake .................. .............. ........... ........... ........... ..... h?17 h-6 parallel eprom loader timing diagram ....... .............. ........... ........... ........... ..... h?17 h-7 eprom parallel bootstrap schematic diagram................................................ h?18 h-8 ram load and execute schematic diagram . .............. ........... ........... ........... ..... h?20 h-9 parallel ram loader timing diagram ................................................................ h?21 h-10 timer relationship ............................................................................................ h?29 i-1 timer relationship ..................................... ........................................................... i?5
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mc68HC05B6 rev. 4.1 freescale xiii list of tables ta bl e number page number title list of tables 1-1 data sheet appendices....................................................................................... 1?1 2-1 mode of operation selection . .............. .............. .............. .............. .............. ........ 2?1 3-1 eeprom control bits descrip tion .......... .............. .............. .............. .............. ..... 3?4 3-2 register outline................................................................................................... 3?8 3-3 irq sensitivity..................................................................................................... 3?9 4-1 i/o pin states ...................................................................................................... 4?2 6-1 method of receiver wake-up . .............. .............. .............. .............. .............. ...... 6?11 6-2 sci clock on sclk pin ..................................................................................... 6?13 6-3 first prescaler stage ......................................................................................... 6?18 6-4 second prescaler stage (transmitter) .......... .............. ........... ........... ........... ...... 6?18 6-5 second prescaler stage (receiver)............... .............. ........... ........... ........... ...... 6?19 6-6 sci baud rate selection .................................................................................... 6?20 8-1 a/d clock selection ................................... .......................................................... 8?4 8-2 a/d channel assignment..................................................................................... 8?5 9-1 effect of reset , por, stop and wait............................................................ 9?5 9-2 interrupt priorities ............................................................................................... 9?7 9-3 irq sensitivity..................................................................................................... 9?9 10-1 mul instruction ................................................................................................ 10?5 10-2 register/memory instructions........................................................................... 10?5 10-3 branch instructions ........................................................................................... 10?6 10-4 bit manipulation instructions............................................................................. 10?6 10-5 read/modify/write instructions ......................................................................... 10?7 10-6 control instructions........................................................................................... 10?7 10-7 instruction set (1 of 2)....................................................................................... 10?8 10-8 instruction set (2 of 2)....................................................................................... 10?9 10-9 m68hc05 opcode map................................................................................... 10?10 11-1 absolute maximum ratings ....................... ........................................................ 11?1 11-2 dc electrical characteristics for 5v operation................................................... 11?2 11-3 dc electrical characteristics for 3.3v operation................................................ 11?5 11-4 a/d characteristics for 5v operation ......... .............. .............. ........... ........... ...... 11?8 11-5 a/d characteristics for 3.3v operation ...... .............. .............. ........... ........... ...... 11?9 11-6 control timing for 5v oper ation ....................................................................... 11?10 11-7 control timing for 3.3v op eration .................................................................... 11?11
freescale xiv mc68HC05B6 rev. 4.1 list of tables ta b l e number page number title 13-1 mc order numbers .............. .............. .............. .............. .............. .............. ....... 13?1 13-2 eproms for pattern generation ................ .............. ........... ............ ........... ....... 13?2 a-1 mode of operation selection ...............................................................................a?1 a-2 register outline ..................................................................................................a?4 a-3 mc68hc05b4 self-check results .............. .........................................................a?6 b-1 register outline ..................................................................................................b?4 c-1 register outline ..................................................................................................c?4 c-2 mode of operation selection ...............................................................................c?8 c-3 bootstrap vector targets in ram ......................................................................c?14 c-4 additional dc electrical characteristi cs for mc68hc705b5.............................c?19 c-5 additional control timing for mc68hc705b5 ....................................................c?19 d-1 mode of operation selection ...............................................................................d?2 d-2 register outline ..................................................................................................d?6 e-1 register outline ..................................................................................................e?4 e-2 eprom control bits description .........................................................................e?6 e-3 eeprom control bits descrip tion ........... .............. .............. .............. ............ ......e?7 e-4 mode of operation selection .............................................................................e?10 e-5 bootstrap vector targets in ram ......................................................................e?18 e-6 absolute maximum ratings ...............................................................................e?21 e-7 dc electrical characteristics for 5v operat ion ............ ........... ........... ............ ....e?22 e-8 dc electrical characteristics for 3.3v o peration ...............................................e?23 e-9 a/d characteristics for 5v operation.................................................................e?24 e-10 a/d characteristics for 3.3v operation..............................................................e?25 e-11 control timing for 5v operation.........................................................................e?26 e-12 control timing for 3.3v operation......................................................................e?27 e-13 dc electrical characteristics for 5v oper ation ......... .............. ........... ............ ....e?28 e-14 control timing for 5v operation.........................................................................e?28 e-15 control timing for 3.3v operation......................................................................e?28 f-1 register outline .................................................................................................. f?4 f-2 eprom control bits description ......................................................................... f?7 f-3 eeprom control bits descrip tion ........... .............. .............. .............. ............ ...... f?8 f-4 mode of operation selection ............................................................................. f?10 f-5 bootstrap vector targets in ram ...................................................................... f?16 f-6 absolute maximum ratings ............................................................................... f?19 f-7 dc electrical characteristics for 5v operat ion ............ ........... ........... ............ .... f?20 f-8 dc electrical characteristics for 3.3v operation ............................................... f?21 f-9 a/d characteristics for 5v operation................................................................. f?22 f-10 a/d characteristics for 3.3v operation.............................................................. f?23 f-11 control timing for 5v operation......................................................................... f?24 f-12 control timing for 3.3v operation...................................................................... f?25 f-13 dc electrical characteristics for 5v oper ation ......... .............. ........... ............ .... f?26 f-14 control timing for 5v operation......................................................................... f?26
mc68HC05B6 rev. 4.1 freescale xv list of tables ta bl e number page number title f-15 control timing for 3.3v op eration ......................................................................f?26 g-1 register outline.................................................................................................. g?4 h-1 register outline.................................................................................................. h?6 h-2 eprom control bits description......................................................................... h?9 h-3 eeprom control bits descrip tion .......... .............. .............. .............. ........... ..... h?10 h-4 mode of operation selection . .............. .............. .............. .............. .............. ..... h?13 h-5 bootstrap vector targets in ram...................................................................... h?19 h-6 absolute maximum ratings .............................................................................. h?22 h-7 dc electrical characteristics for 5v operation.................................................. h?23 h-8 dc electrical characteristics for 3.3v operation............................................... h?24 h-9 a/d characteristics for 5v operation ......... .............. .............. ........... ........... ..... h?25 h-10 a/d characteristics for 3.3v operation ...... .............. .............. ........... ........... ..... h?26 h-11 control timing for 5v oper ation ........................................................................ h?27 h-12 control timing for operation at 3.3v ....... .......................................................... h?28 h-13 dc electrical characteristics for 5v operation.................................................. h?29 h-14 control timing for 5v oper ation ........................................................................ h?29 h-15 control timing for 3.3v op eration ..................................................................... h?29 i-1 ordering information............................................................................................ i?1 i-2 dc electrical characteristics for 5v operation...................................................... i?2 i-3 a/d characteristics for 5v operation ......... .............. .............. .............. ........... ...... i?3
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mc68HC05B6 rev. 4.1 freescale 1-1 introduction 1 1 introduction the mc68HC05B6 microcomputer (mcu) is a me mber of freescale?s mc68hc05 family of low-cost single chip microcomputers. this 8-bit mcu contains an on-chip oscillator, cpu, ram, rom, eeprom, a/d converter, pulse length m odulated outputs, i/o, serial communications interface, programmable timer system and watchdog. the fully static design allows operation at frequencies down to dc to further reduce the already low power consumption to a few micro-amps. this data sheet is structured su ch that devices similar to the mc68HC05B6 are described in a set of appendices (see ta b l e 1 - 1 ). table 1-1 data sheet appendices device appendix differences from mc68HC05B6 mc68hc05b4 a 4k bytes rom; no eeprom mc68hc05b8 b 7.25k bytes rom mc68hc705b5 c 6k bytes eprom; self-check replaced by bootstrap firmware; no eeprom mc68hc05b16 d 16k bytes rom; increased ram and self-check rom mc68hc705b16 e 16k bytes eprom; increased ram; self-check replaced by bootstrap firmware; modified power-on reset routine mc68hc705b16n f 16k bytes eprom; increased ram; self-check replaced by bootstrap firmware; modified power-on reset routine mc68hc05b32 g 32k bytes rom; no page zero rom; increased ram mc68hc705b32 h 32k bytes eprom; no page zero rom; increased ram; self-check mode replaced by bootstrap firmware
freescale 1-2 mc68HC05B6 rev. 4.1 introduction 1 1.1 features hardware features fully static design featuring the industry standard m68hc05 family cpu core on chip crystal oscillator with divide by 2 or a software selectable divide by 32 option (slow mode) 2.1 mhz internal operating frequency at 5v; 1.0 mhz at 3v high speed version available 176 bytes of ram 5936 bytes of user rom plus 14 bytes of user vectors 256 bytes of byte erasable eeprom with internal charge pump and security bit write/erase protect bit for 224 of the 256 bytes eeprom self test/bootstrap mode power saving stop, wait and slow modes three 8-bit parallel i/o ports and one 8-bit input-only port software option available to output the internal e-clock to port pin pc2 16-bit timer with 2 input c aptures and 2 output compares computer operating properly (cop) watchdog timer serial communications interface system (sci) with independent transmitter/receiver baud rate selection; receiver wake-up function for use in multi-receiver systems 8 channel a/d converter 2 pulse length modulation systems wh ich can be used as d/a converters one interrupt request input plus 4 on-board hardware interrupt sources available in 52-pin plastic leaded chip carrier (plcc), 64-pin quad flat pack (qfp) and 56-pin shrink dual in line (sdip) packages complete development system support availabl e using the mmds05 development station with the m68hc05b32em emulation module extended operating temperature range of -40 to +125 c
mc68HC05B6 rev. 4.1 freescale 1-3 introduction 1 1.2 mask options for the mc68HC05B6 the mc68HC05B6 has three mask options that are programmed during manufacture and must be specified on the order form. power-on-reset delay (t porl ) = 16 or 4064 cycles automatic watchdog enable/disable following a power-on or external reset watchdog enable/disable during wait mode warning: it is recommended that an exter nal clock is always used if t porl is set to 16 cycles. this will prevent any problems arising with osci llator stability when the device is put into stop mode. figure 1-1 mc68HC05B6 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit programmable timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator 176 bytes ram cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp1 256 bytes eeprom charge pump 2 / 32 plma d/a plmb d/a 8-bit 432 bytes user rom 5950 bytes self check rom (including 14 bytes user vectors)
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mc68HC05B6 rev. 4.1 freescale 2-1 modes of operation and pin descriptions 2 2 modes of operation and pin descriptions 2.1 modes of operation the mc68HC05B6 mcu has two modes of operation, namely single chip and self check modes. ta bl e 2 - 1 shows the conditions required to enter each mode on the rising edge of reset . 2.1.1 single chip mode this is the normal operating mode of the mc68hc0 5b6. in this mode the device functions as a self-contained microcomputer (mcu) with all on-boa rd peripherals, including the three 8-bit i/o ports and the 8-bit input-only port, available to the user. all address and data activity occurs within the mcu. table 2-1 mode of operation selection irq pin tcap1 pin pd3 pd4 mode v ss to v dd v ss to v dd x x single chip 2v dd v dd 1 0 serial ram loader 2v dd v dd 1 1 jump to any address
freescale 2-2 mc68HC05B6 rev. 4.1 modes of operation and pin descriptions 2 2.2 serial ram loader the ?load program in ram and execute? mode is en tered if the following conditions are satisfied when the reset pin is released to v dd . the format used is identical to the format used for the mc68hc805c4. the sec bit in the options register must be inactive, i.e. set to ?1?. ?irq at 2xv dd ? tcap1 at v dd ?pd3 at v dd for at least 30 mach ine cycles after reset ?pd4 at v ss for at least 30 machine cycles after reset in the ?load program in ram and execute? routine, user programs are loaded into mcu ram via the sci port and then executed. data is loaded sequ entially, starting at ram location $0050, until the last byte is loaded. program control is then transferred to the ram program starting at location $0051. the first byte loaded is the count of the total number of by tes in the program plus the count byte. the program starts at the second byte in ram. during the firmware initialization stage, the sci is configured for the nrz data format (idle line, start bit, eight data bits and stop bit). the baud rate is 9600 with a 4 mhz crystal. a program to convert ascii s-records to the format required by the ram loader is available from freescale. if immediate execution is not desired after loadin g the ram program, it is possible to hold off execution. this is accomplished by setting the byte count to a value that is greater than the overall length of the loaded data. when the last byte is loaded, the firmware will halt operation expecting additional data to arrive. at this point, the reset switch is placed in the reset position which will reset the mcu, but keep the ram program intact. all routines can now be entered from this state, including the one which will execute the program in ram (see section 2.3 ). to load a program in the eeprom, the ?load prog ram in ram and execute? function is also used. in this instance the process involves two distinct steps. firstly, the ram is loaded with a program which will control the loading of the eeprom, and when the ram contents are executed, the mcu is instructed to load the eeprom. the erased state of the eeprom is $ff. figure 2-1 shows the schematic diagram of the circuit required for the serial ram loader.
mc68HC05B6 rev. 4.1 freescale 2-3 modes of operation and pin descriptions 2 figure 2-1 mc68HC05B6 ?load program in ram and execute? schematic diagram 32 osc1 osc2 irq tcap2 tcmp2 tcap1 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 vss pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 reset vdd 18 24 25 26 27 28 29 30 31 16 17 19 41 10 k ? 0.01 f 10 nf 47 f 10 m ? 4 mhz 22 pf 22 pf p1 gnd +5v 2xv dd reset 10 vrh vrl vpp1 plma plmb tcmp1 rdi tdo nc nc rs232 level translator suggested: mc145406 or max232 9600 bd rs232 sclk 10 k ? 11 9 22 8 7 40 20 21 51 1 23 2 3 4 5 12 13 14 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 6 15 50 52 connect as required for the application connect as required for the application mc68HC05B6 (52-pin package)
freescale 2-4 mc68HC05B6 rev. 4.1 modes of operation and pin descriptions 2 2.3 ?jump to any address? the ?jump to any address? mode is entered when the reset pin is released to v dd , if the following conditions are satisfied: ?irq at 2xv dd ? tcap1 at v dd ?pd3 at v dd for at least 30 mach ine cycles after reset ?pd4 at v dd for at least 30 mach ine cycles after reset this function allows execution of programs previously loaded in ram or eeprom using the methods outlined in section 2.2 . to execute the ?jump to any address? function, dat a input at port a has to be $cc and data input at port b and port c should represent the msb and lsb respectively, of the address to jump to for execution of the user program. a schematic diagram of the circuit required is shown in figure 2-2 .
mc68HC05B6 rev. 4.1 freescale 2-5 modes of operation and pin descriptions 2 figure 2-2 mc68HC05B6 ?jump to any address? schematic diagram 32 osc1 osc2 irq tcap2 tcmp2 tcap1 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 vss pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 reset vdd 18 24 25 26 27 28 29 30 31 16 17 19 41 10 k ? 0.01 f 10 nf 47 f 10 m ? 4 mhz 22 pf 22 pf p1 gnd +5v 2xv dd reset 10 vrh vrl vpp1 plma plmb tcmp1 rdi tdo nc nc sclk 10 k ? 11 9 22 8 7 40 20 21 51 1 23 2 3 4 5 12 13 14 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 6 15 50 52 connect as required for the application 8 x 10 k ? optional (see note) 8 x 10 k ? 8 x 10 k ? msb lsb select required address note: these eight resistors are optional ; direct connection is possible if pins pa0-pa7, pb0-pb7 and pc0-pc7 are kept in input mode during application. mc68HC05B6 (52-pin package)
freescale 2-6 mc68HC05B6 rev. 4.1 modes of operation and pin descriptions 2 2.4 low power modes the stop and wait instructions have different effects on the programmable timer, the serial communications interface, the watchdog syst em, the eeprom and the a/d converter. these different effects are described in the following sections. 2.4.1 stop the stop instruction places the mcu in its lowe st power consumption mode. in stop mode, the internal oscillator is turned off, halting all internal processing including timer, serial communications interface and the a/d converter (see flowchart in figure 2-3 ). the only way for the mcu to wake-up from the stop mode is by receipt of an external interrupt or by the detection of a reset (logic low on reset pin or a power-on reset). during stop mode, the i-bit in the ccr is cleared to enable external interrupts (see section 10.1.5 ). the sm bit is cleared to allow nomin al speed operation for the 4064 cycles count while exiting stop mode (see section 2.4.3 ). all other registers and memory remain unaltered and all input/output lines remain unchanged. this continues until an external interrupt (irq ) or reset is sensed, at which time the internal oscillator is turned on. the external interrupt or reset causes the program counter to vector to the corresponding locations ($1ffa, b and $1ffe, f respectively). when leaving stop mode, a t porl internal cycles delay is provid ed to give the oscillator time to stabilise before releasing cpu operation. this del ay is selectable via a mask option to be either 16 or 4064 cycles. the cpu will resume operation by servicing the interrupt that wakes it up, or by fetching the reset vector, if reset wakes it up. warning: if t porl is selected to be 16 cycles, it is re commended that an exte rnal clock signal is used to avoid problems with oscillator stab ility while the device is in stop mode. note: the stacking corresponding to an eventual interrupt to go out of stop mode will only be executed when going out of stop mode. the following list summarizes the effect of stop mode on the individual modules of the mc68HC05B6. ? the watchdog timer is reset; refer to section 9.1.4.1 ? the eeprom acts as read-only memory (rom); refer to section 3.6 ? all sci activity stopped; refer to section 6.13 ? the timer stops counting; refer to section 5.6 ? the plm outputs remain at current level; refer to section 7.3 ? the a/d converter is disabled; refer to section 8.3 ? the i-bit in the ccr is cleared
mc68HC05B6 rev. 4.1 freescale 2-7 modes of operation and pin descriptions 2 figure 2-3 stop and wait flowcharts timer interrupt? irq external interrupt? sci interrupt? stop oscillator and all clocks. clear i bit. stop wait reset? irq external interrupt? generate watchdog reset reset? watchdog active? (1) fetch reset vector or (2) service interrupt: a. stack b. set i-bit c. vector to interrupt routine (1) fetch reset vector or (2) service interrupt: a. stack b. set i-bit c. vector to interrupt routine turn on oscillator. wait for time delay to stabilise restart processor clock yes no yes yes yes yes yes yes no no no no no no oscillator active. timer, sci, a/d, eeprom clocks active. processor clocks stopped clear i-bit
freescale 2-8 mc68HC05B6 rev. 4.1 modes of operation and pin descriptions 2 2.4.2 wait the wait instruction places the mcu in a low power consumption mode, but wait mode consumes more power than stop mode. all cp u action is suspended and the watchdog is disabled, but the timer, a/d and sci systems remain active and operate as normal (see flowchart in figure 2-3 ). all other memory and registers remain unaltered and all parallel input/output lines remain unchanged. the programmi ng or erase mechanism of the eeprom is also unaffected, as well as the charge pump high voltage generator. during wait mode the i-bit in the ccr is cleared to enable all interrupts. the inte bit in the miscellaneous register ( section 2.5 ) is not affected by wait mode. when any interrupt or reset is sensed, the program counter vect ors to the locations containing the start address of the interrupt or reset service routine. any irq , timer (overflow, input capture or output compare) or sci interrupt (in addition to a logic low on the reset pin) causes the processor to exit wait mode. if a non-reset exit from wait mode is performed (i.e . timer overflow interrupt exit), the state of the remaining systems will be unchanged. if a reset exit from wait mode is performed t he entire system reverts to the disabled reset state. note: the stacking corresponding to an eventual interrupt to leave wait mode will only be executed when leaving wait mode. the following list summarizes the effect of wait mode on the modules of the mc68HC05B6. ? the watchdog timer functions according to the mask option selected; refer to section 9.1.4.2 ? the eeprom is not affected; refer to section 3.7 ? the sci is not affected; refer to section 6.14 ? the timer is not affected; refer to section 5.7 ? the plm is not affected; refer to section 7.4 ? the a/d converter is not affected; refer to section 8.4 ? the i-bit in the ccr is cleared 2.4.2.1 power consumption during wait mode power consumption during wait mode depends on how many systems are active. the power consumption will be highe st when all the systems (a/d, timer, eeprom and sci) are active, and lowest when the eeprom erase and programmin g mechanism, sci and a/d are disabled. the timer cannot be disabled in wait mode. it is important that before entering wait mode, the programmer sets the relevant control bits fo r the individual modules to reflect the desired functionality during wait mode. power consumption may be further re duced by the use of slow mode.
mc68HC05B6 rev. 4.1 freescale 2-9 modes of operation and pin descriptions 2 2.4.3 slow mode the slow mode function is controlled by the sm bit in the miscellaneous register at location $000c. it allows the user to insert, under softw are control, an extra divide-by-16 between the oscillator and the internal clock driver (see figure 2-4 ). this feature permits a slow down of all the internal operations and thus reduces power cons umption. the slow mode function should not be enabled while us ing the a/d converter or while eras ing/programming the eeprom unless the internal a/d rc oscillator is turned on. 2.4.3.1 miscella neous register sm ? slow mode 1 (set) ? the system runs at a bus speed 16 times lower than normal (f osc /32). slow mode affects all sections of the device, including sci, a/d and timer. 0 (clear) ? the system runs at normal bus speed (f osc /2). the sm bit is cleared by external or power-on reset. the sm bit is automatically cleared when entering stop mode. note: the bits shown shaded in the above representation are explained individually in the relevant sections of this manual. the comple te register plus an explanation of each bit can be found in section 3.8 . figure 2-4 slow mode divider block diagram address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous $000c por intp intn inte sfa sfb sm wdog ?001 000? osc1 pin osc2 pin oscillator f osc control logic sm?bit f osc /2 2 16 main internal clock f osc /32 (bit 1, $000c)
freescale 2-10 mc68HC05B6 rev. 4.1 modes of operation and pin descriptions 2 2.5 pin descriptions 2.5.1 vdd and vss power is supplied to the microcontroller using t hese two pins. vdd is the positive supply and vss is ground. it is in the nature of cm os designs that very fast signal transitions occur on the mcu pins. these short rise and fall times place very high short-duration current demands on the power supply. to prevent noise problems, special care must be ta ken to provide good power supply by-passing at the mcu. by-pass capacitors should have good high-frequency characteristics and be as close to the mcu as possible. bypassing requirements vary , depending on how heavily the mcu pins are loaded. 2.5.2 irq this is an input-only pin for external interrupt sources. interrupt triggering is selected using the intp and intn bits in the miscellaneous register, to be one of four options detailed in ta b l e 9 - 3 . in addition, the external interrupt facility (irq ) can be disabled using the inte bit in the miscellaneous register (see section 3.8 ). it is only possible to change the interrupt option bits in the miscellaneous register while the i-bit is se t. selecting a different interrupt option will automatically clear any pending interrupts. further details of the external interrupt procedure can be found in section 9.2.3.1 . the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. 2.5.3 reset this active low i/o pin is used to reset the mcu. applying a logic zero to this pin forces the device to a known start-up state. an external rc-circui t can be connected to this pin to generate a power-on-reset (por) if required. in this case, the time constant must be great enough to allow the oscillator circuit to stabilize. this input has an internal schmitt trigger to improve noise immunity. when a reset condition occurs internally, i.e. from the cop watchdog, the reset pin provides an active-low open drain output signal that may be used to reset external hardware. 2.5.4 tcap1 the tcap1 input controls the in put capture 1 function of the on-chip programmable timer system.
mc68HC05B6 rev. 4.1 freescale 2-11 modes of operation and pin descriptions 2 2.5.5 tcap2 the tcap2 input controls the input capture 2 fu nction of the on-chip programmable timer system. 2.5.6 tcmp1 the tcmp1 pin is the output of the output compare 1 function of the timer system. 2.5.7 tcmp2 the tcmp2 pin is the output of the output compare 2 function of the timer system. 2.5.8 osc1, osc2 these pins provide control input for an on-chip oscillator circuit. a crystal, ceramic resonator or external clock signal connected to these pins suppl ies the oscillator clock. the oscillator frequency (f osc ) is divided by two to give the internal bus frequency (f op ). there is also a software option which introduces an additional divide by 16 into the oscillator clock, giving an internal bus frequency of f osc /32. 2.5.8.1 crystal the circuit shown in figure 2-5 (a) is recommended when using either a crystal or a ceramic resonator. figure 2-5 (d) lists the recommended capacitance and feedback resistance values. the internal oscillator is designed to interface with an at-cut parallel-resonant quartz crystal resonator in the frequency range specified for f osc (see section 11.4 ). use of an external cmos oscillator is recommended when crystals outside the specified ranges are to be used. the crystal and associated components should be mounted as close as possible to the input pins to minimise output distortion and start-up st abilisation time. the manufacturer of the particular crystal being considered should be consulted for specific information. 2.5.8.2 ceramic resonator a ceramic resonator may be used instead of a crystal in cost sensitive applications. the circuit shown in figure 2-5 (a) is recommended when using either a crystal or a ceramic resonator. figure 2-5 (d) lists the recommended capacitance and feedback resistance values. the manufacturer of the particular ceramic resonator being considered s hould be consulted for specific information.
freescale 2-12 mc68HC05B6 rev. 4.1 modes of operation and pin descriptions 2 2.5.8.3 external clock an external clock should be applied to the osc1 input, with the osc2 pin left unconnected, as shown in figure 2-5 (c). the t oxov or t ilch specifications (see section 11.4 ) do not apply when using an external clock input. the equivalent sp ecification of the external clock source should be used in lieu of t oxov or t ilch . figure 2-5 oscillator connections ceramic resonator 2 ? 4mhz unit r s (typ) 10 ? c 0 40 pf c 1 4.3 pf c osc1 30 pf c osc2 30 pf r p 1 ? 10 m ? q 1250 ? crystal 2mhz 4mhz unit r s (max) 400 75 ? c 0 57pf c 1 812 ? f c osc1 15 ? 40 15 ? 30 pf c osc2 15 ? 30 15 ? 25 pf r p 10 10 m ? q 30 000 40 000 ? osc1 osc2 mcu c osc2 c osc1 osc1 osc2 mcu nc external clock osc1 osc2 r s c 1 l c 0 (d) typical crystal and ce ramic resonator parameters (c) external clock source connections (b) crystal equivalent circuit (a) crystal/ceramic resonator oscillator connections r p
mc68HC05B6 rev. 4.1 freescale 2-13 modes of operation and pin descriptions 2 2.5.9 rdi (receive data in) the rdi pin is the input pin of the sci receiver. 2.5.10 tdo (tr ansmit data out) the tdo pin is the output pin of the sci transmitter. 2.5.11 sclk the sclk pin is the clock output pin of the sci transmitter. 2.5.12 plma the plma pin is the output of pu lse length modulation converter a. 2.5.13 plmb the plmb pin is the output of pu lse length modulation converter b. 2.5.14 vpp1 the vpp1 pin is the output of th e charge pump for the eeprom1 array. 2.5.15 vrh the vrh pin is the positive refere nce voltage for the a/d converter. 2.5.16 vrl the vrl pin is the negative reference voltage for the a/d converter. 2.5.17 pa0 ? pa7/pb0 ? pb7/pc0 ? pc7 these 24 i/o lines comprise ports a, b and c. th e state of any pin is software programmable, and all the pins are configured as inpu ts during power-on or reset. under software control the pc2 pin can output the internal e-clock (see section 4.2 ). 2.5.18 pd0/an0?pd7/an7 this 8-bit input only port (d) shares its pins with the a/d converter. when enabled, the a/d converter uses pins pd0/an0 ? pd7/an7 as its analog inputs. on reset, the a/d converter is disabled which forces the port d pins to be input only port pins (see section 8.5 ).
freescale 2-14 mc68HC05B6 rev. 4.1 modes of operation and pin descriptions 2 this page left bl ank intentionally
mc68HC05B6 rev. 4.1 freescale 3-1 memory and registers 3 3 memory and registers the mc68HC05B6 mcu is capable of addressing 8192 bytes of memory and registers with its program counter. the memory map includes 5950 bytes of user rom (including user vectors), 432 bytes of self check rom, 176 bytes of ram and 256 bytes of eeprom. 3.1 registers all the i/o, control and status registers of t he mc68HC05B6 are contained within the first 32-byte block of the memory map, as shown in figure 3-1 . the miscellaneous register is shown in section 3.8 as this register contains bits which are relevant to several modules. 3.2 ram the user ram comprises 176 bytes of memory, from $0050 to $00ff. this is shared with a 64 byte stack area. the stack begins at $00ff and may extend down to $00c0. note: using the stack area for data storage or tem porary work locations requires care to prevent the data from being overwritten due to stac king from an interrupt or subroutine call. 3.3 rom the user rom consists of 5950 bytes of rom mapped as follows: 48 bytes of page zero rom from $0020 to $004f 5888 bytes of user rom from $0800 to $1eff 14 bytes of user vectors from $1ff2 to $1fff
freescale 3-2 mc68HC05B6 rev. 4.1 memory and registers 3 3.4 self-check rom there are two areas of self-check rom (romi and romii) located from $0200 to $02bf (192 bytes) and $1f00 to $1fef (240 bytes) respectively. figure 3-1 memory map of the mc68HC05B6 $1ffe?f $1ff6?7 port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register user vectors (14 bytes) $0000 i/o (32 bytes) $0020 $00c0 $0100 $1ff0 stack ram (176 bytes) $02c0 $0200 $1f00 $0050 port a data direction register port b data direction register port c data direction register eeprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f page 0 user rom (48 bytes) self-check rom i (192 bytes) user rom (5888 bytes) self-check rom ii (240 bytes) $0800 $1ff2?3 optr (1 byte) non protected (31 bytes) protected (224 bytes) eeprom (256 bytes) $0101 $0120 $0100 options register reserved mc68HC05B6 registers sci timer overflow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $1ff4?5 $1ff8?9 $1ffa?b $1ffc?d
mc68HC05B6 rev. 4.1 freescale 3-3 memory and registers 3 3.5 eeprom the user eeprom consists of 256 bytes of me mory located from address $0100 to $01ff. 255 bytes are general purpose and 1 byte is used by the option register. the non-volatile eeprom is byte erasable. an internal charge pump provides the eeprom voltage (v pp1 ), which removes the need to supply a high voltage for erase and programming functions. the charge pump is a capacitor/diode ladder network which will give a very high impedance output of around 20-30 m ? . the voltage of the charge pump is visible at the vpp1 pin. du ring normal operation of the device, where programming/erasing of the eeprom array will o ccur, vpp1 should never be connected to either vdd or vss as this could prev ent the charge pump reaching t he necessary programming voltage. where it is considered dangerous to leave vpp1 unconnected for reasons of excessive noise in a system, it may be tied to v dd ; this will protect the eeprom data but will also increase power consumption, and therefore it is recommended that the protect bit function is used for regular protection of eeprom data (see section 3.5.5 ). in order to achieve a higher degree of security for stored data, there is no c apability for bulk or row erase operations. the eeprom control register ($0007) provides control of the eeprom programming and erase operations. warning: the vpp1 pin should never be connected to vss, as this could cause permanent damage to the device. 3.5.1 eeprom control register eclk see section 4.3 for a description of this bit. e1era ? eeprom erase/programming bit providing the e1lat and e1pgm bits are at logic one, this bit indicates whether the access to the eeprom is for erasing or programming purposes. 1 (set) ? an erase operation will take place. 0 (clear) ? a programming operation will take place. once the program/erase eeprom address has been selected, e1era cannot be changed. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eeprom/eclk control $0007 0 0 0 0 eclk e1era e1lat e1pgm 0000 0000
freescale 3-4 mc68HC05B6 rev. 4.1 memory and registers 3 e1lat ? eeprom programming latch enable bit 1 (set) ? address and data can be latched into the eeprom for further program or erase operations, prov iding the e1pgm bit is cleared. 0 (clear) ? data can be read from the eeprom. the e1era bit and the e1pgm bit are reset to zero when e1lat is ?0?. stop, power-on and external reset clear the e1lat bit. note: after the t era1 erase time or t prog1 programming time, the e1lat bit has to be reset to zero in order to clear the e1era bit and the e1pgm bit. e1pgm ? eeprom charge pump enable/disable 1 (set) ? internal charge pump generator switched on. 0 (clear) ? internal charge pump generator switched off. when the charge pump generator is on, the resulting hi gh voltage is applied to the eeprom array. this bit cannot be set before the data is selected, and once this bit has been set it can only be cleared by clearing the e1lat bit. a summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are give in ta b l e 3 - 1 . note: all combinations are not shown in the above table, since the e1pgm and e1era bits are cleared when the e1lat bit is at zero, and will result in a read condition. table 3-1 eeprom control bits description e1era e1lat e1pgm description 0 0 0 read condition 0 1 0 ready to load address/data for program/erase 0 1 1 byte programming in progress 1 1 0 ready for byte erase (load address) 1 1 1 byte erase in progress
mc68HC05B6 rev. 4.1 freescale 3-5 memory and registers 3 3.5.2 eeprom read operation to be able to read from eeprom, the e1lat bit has to be at logic zero, as shown in ta b l e 3 - 1 . while this bit is at logic zero, the e1pgm bit and the e1era bit are permanently reset to zero and the 256 bytes of eeprom may be read as if it we re a normal rom area. the internal charge pump generator is automatically switched off since the e1pgm bit is reset. if a read operation is executed while the e1lat bit is set (erase or programming sequence), data resulting from the operation will be $ff. note: when not performing any programming or er ase operation, it is recommended that eeprom should remain in the read mode (e1lat = 0) 3.5.3 eeprom erase operation to erase the contents of a byte of t he eeprom, the following steps should be taken: 1 set the e1lat bit. 1) set the e1era bit (1& 2 may be done simultaneously with the same instruction). 2) write address/data to the eepr om address to be erased. 3) set the e1pgm bit. 4) wait for a time t era1 . 5) reset the e1lat bit (to logic zero). while an erase operat ion is being performed, any acce ss of the eeprom array will not be successful. the erased state of the eeprom is $f f and the programmed state is $00. note: data written to the address to be erased is not used, therefore its value is not significant. if a second word is to be erased, it is important that the e1lat bit be reset before restarting the erasing sequence otherwise any write to a new address will have no effect. this condition provides a higher degree of security for the stored data. user programs must be running from the ram or rom as the eeprom will have its address and data buses latched.
freescale 3-6 mc68HC05B6 rev. 4.1 memory and registers 3 3.5.4 eeprom programming operation to program a byte of eeprom, t he following steps should be taken: 1 set the e1lat bit. 2 write address/data to the eepr om address to be programmed. 3 set the e1pgm bit. 4 wait for time t prog1 . 5 reset the e1lat bit (to logic zero). while a programming operation is being performed, any access of the eeprom array will not be successful. warning: to program a byte correctly, it has to have b een previously erased. it is advised that this is done only for 0 1 transitions, as this saves excessive overwriting of eeprom. if a second word is to be programmed, it is im portant that the e1lat bit be reset before restarting the programming sequence otherwise any write to a new address will have no effect. this condition provides a higher degree of security for the stored data. user programs must be running from the ram or rom as the eeprom will have its address and data buses latched. note: 224 bytes of eeprom (address $0120 to $01ff) can be program and erase protected under the control of bit 1 of the optr register detailed in section 3.5.5 . 3.5.5 options register (optr) this register (optr), located at $0100, cont ains the secure and protect functions for the eeprom and allows the user to select options in a non-volatile manner. the contents of the optr register are loaded into data latches with each power-on or external reset. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset options (optr) (1) (1) this register is implemented in eeprom; theref ore reset has no effect on the individual bits. $0100 ee1p sec not affected
mc68HC05B6 rev. 4.1 freescale 3-7 memory and registers 3 ee1p ? eeprom protect bit in order to achieve a higher degr ee of protection, the eeprom is effectively split into two parts, both working from the vpp1 charge pump. part 1 of the eeprom array (32 bytes from $0100 to $011f) cannot be protected; part 2 (224 bytes from $0120 to $01ff) is protected by the ee1p bit of the options register. 1 (set) ? part 2 of the eeprom array is not protected; all 256 bytes of eeprom can be accessed for any read, erase or programming operations 0 (clear) ? part 2 of the eeprom array is protected; any attempt to erase or program a location will be unsuccessful when this bit is set to 1 (erased), the protection will remain until the next power-on or external reset. ee1p can only be written to ?0? when the el at bit in the eeprom control register is set. sec ? security bit this high security bit allows th e user to secure th e eeprom data from ex ternal accesses. when the sec bit is at ?0?, the eeprom contents are se cured by preventing any entry to test mode. the only way to erase the sec bit to ?1? externally is to enter self-check mode, at which time the entire eeprom contents will be erased. when the sec bit is changed, its new value will have no effect until the next external or power-on reset. 3.6 eeprom during stop mode when entering stop mode, the eeprom is autom atically set to the read mode and the vpp1 high voltage charge pump generator is automatically disabled. 3.7 eeprom during wait mode the eeprom is not affected by wait mode. an y program/erase operati on will continue as in normal operating mode. the charge pump is not af fected by wait mode, therefore it is possible to wait the t era1 erase time or t prog1 programming time in wait mode. under normal operating conditions, the charge pum p generator is driven by the internal cpu clocks. when the operating frequency is low, e.g. during wait mode, the clocking should be done by the internal a/d rc oscillator. the rc oscillator is enabled by setting the adrc bit of the a/d status/control register at $0009.
freescale 3-8 mc68HC05B6 rev. 4.1 memory and registers 3 table 3-2 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 undefined port b data (portb) $0001 undefined port c data (portc) $0002 pc2/ eclk undefined port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 undefined port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eeprom/eclk control $0007 0 0 0 0 eclk e1era e1lat e1pgm 0000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl undefined sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 undefined input capture high 1 $0014 undefined input capture low 1 $0015 undefined output compare high 1 $0016 undefined output compare low 1 $0017 undefined timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c undefined input capture low 2 $001d undefined output compare high 2 $001e undefined output compare low 2 $001f undefined options (optr) (3) $0100 ee1p sec not affected (1) the por bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) this register is implemented in eeprom; theref ore reset has no effect on the individual bits.
mc68HC05B6 rev. 4.1 freescale 3-9 memory and registers 3 3.8 miscellaneous register por ? power-on reset bit (see section 9.1 ) this bit is set each time the device is powered on. therefore, the state of the por bit allows the user to make a software distinction between a power-on and an external reset. this bit cannot be set by software and is cleared by writing it to zero. 1 (set) ? a power-on reset has occurred. 0 (clear) ? no power-on reset has occurred. intp, intn ? external interr upt sensitivity options (see section 9.2 ) these two bits allow the user to select which edge the irq pin will be sensitive to (see ta bl e 3 - 3 ). both bits can be written to only while the i-bit is set, and are cleared by power-on or external reset, thus the device is initialised with n egative edge and low level sensitivity. inte ? external interrupt enable (see section 9.2 ) 1 (set) ? external interrupt function (irq ) enabled. 0 (clear) ? external interrupt function (irq ) disabled. the inte bit can be written to only while the i-bit is set, and is set by power-on or external reset, thus enabling the external interrupt function. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous $000c por (1) (1) the por bit is set each time there is a power-on reset. intp intn inte sfa sfb sm wdog (2) (2) the state of the wdog bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled. ?001 000? table 3-3 irq sensitivity intp intn irq sensitivity 0 0 negative edge and low level sensitive 0 1 negative edge only 1 0 positive edge only 1 1 positive and negative edge sensitive
freescale 3-10 mc68HC05B6 rev. 4.1 memory and registers 3 sfa ? slow or fast mode selection for plma (see section 7.1 ) this bit allows the user to select the slow or fast mode of the plma pulse length modulation output. 1 (set) ? slow mode plma (4096 x timer clock period). 0 (clear) ? fast mode plma (256 x timer clock period). sfb ? slow or fast mode selection for plmb (see section 7.1 ) this bit allows the user to select the slow or fast mode of the plmb pulse length modulation output. 1 (set) ? slow mode plmb (4096 x timer clock period). 0 (clear) ? fast mode plmb (256 x timer clock period). note: the highest speed of the plm system corr esponds to the frequency of the tof bit being set, multiplied by 256. the lowest speed of the plm system corresponds to the frequency of the tof bit being set, multiplied by 16. warning: because the sfa bit and sfb bit are not double buffered, it is mandatory to set the sfa bit and sfb bit to the desired values before writing to the plm registers; not doing so could temporarily give incorrect values at the plm outputs. sm ? slow mode (see section 2.4.3 ) 1 (set) ? the system runs at a bus speed 16 times lower than normal (f osc /32). slow mode affects all sect ions of the device, including sci, a/d and timer. 0 (clear) ? the system runs at normal bus speed (f osc /2). the sm bit is cleared by external or power-on reset. the sm bit is aut omatically cleared when entering stop mode. wdog ? watchdog enable/disable (see section 9.1.4 ) the wdog bit can be used to enable the watchdog timer previously disabled by a mask option. following a watchdog reset the state of the wdog bit is as defined by the mask option specified. once the watchdog is enabled, the wdog bit acts as a reset mechanism for the watchdog counter. writing a?1? to this bit clears the coun ter to its initial value and prevents a watchdog timeout. 1 (set) ? watchdog counter cleared and enabled. 0 (clear) ? the watchdog cannot be disabled by software; writing a zero to this bit has no effect.
mc68HC05B6 rev. 4.1 freescale 4-1 input/output ports 4 4 input/output ports in single-chip mode, the mc68HC05B6 has a total of 24 i/o lines, arranged as three 8-bit ports (a, b and c), and eight input-only lines, arranged as one 8-bit port (d). each i/o line is individually programmable as either input or output, under the software control of the data direction registers. the 8-bit input-only port (d) shares its pins with the a/d converter, when the a/d converter is enabled. to avoid glitches on the output pins, da ta should be written to the i/o port data register before writing ones to the corresponding data direction register bits to set the pins to output mode. 4.1 input/output programming the bidirectional port lines may be programmed as inputs or outputs under software control. the direction of each pin is determined by the state of the corresponding bit in the port data direction register (ddr). each port has an associated ddr. any i/o port pin is configured as an output if its corresponding ddr bit is set to a logic one. a pin is configured as an input if its corresponding ddr bit is cleared to a logic zero. at power-on or reset, all ddrs are cleared, thus configuring all port pins as inputs. the data direction registers can be written to or read by the mcu. during the pr ogrammed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. the operation of the standard port hardware is shown schematically in figure 4-1 .
freescale 4-2 mc68HC05B6 rev. 4.1 input/output ports 4 ta b l e 4 - 1 shows the effect of reading from or writing to an i/o pin in various circumstances. note that the read/write signal shown is internal and not available to the user. 4.2 ports a and b these ports are standard m68hc05 bidirectional i/ o ports, each comprising a data register and a data direction register. reset does not affect the state of the data regist er, but clears the data direction register, thereby returning all port pins to input mode. writing a ?1? to any ddr bit sets the corresponding port pin to output mode. figure 4-1 standard i/o port structure table 4-1 i/o pin states r/w ddrn action of mcu write to/read of data bit 0 0 the i/o pin is in input mode. data is written into the output data latch. 0 1 data is written into the output data latch, and output to the i/o pin. 1 0 the state of the i/o pin is read. 1 1 the i/o pin is in output mode. the output data latch is read. latched data register bit ddrn data input buffer output buffer o/p data buffer m68hc05 internal connections ddrn data i/o pin 100 111 0 0 tristate 0 1 tristate i/o pin output ? ? input data direction register bit ? ? ? ?
mc68HC05B6 rev. 4.1 freescale 4-3 input/output ports 4 4.3 port c in addition to the standard port functions described for port a and b, port c pin 2 can be configured, using the eclk bit of the eeprom/eclk control register, to output the cpu clock. if this is selected the corresponding ddr bit is automatically set and bit 2 of port c will always read the output data latch. the other port c pi ns are not affected by this feature. eclk ? external clock output bit 1 (set) ? eclk cpu clock is output on pc2. 0 (clear) ? eclk cpu clock is not output on pc2; port c acts as a normal i/o port. the eclk bit is cleared by power-on or external re set. it is not affected by the execution of a stop or wait instruction. the timing diagram of the clock output is shown in figure 4-2 . 4.4 port d this 8-bit input-only port shares its pins with the a/d converter subsystem. when the a/d converter is enabled, pins pd0-pd7 read the eight analog inputs to the a/d converter. port d can be read at any time, however, if it is read during an a/d conversion sequence noise, may be injected on the analog inputs, resulting in reduced accuracy of the a/d. furthermore, performing address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eeprom/eclk control $0007 0 0 0 0 eclk e1era e1lat e1pgm 0000 0000 figure 4-2 eclk timing diagram internal clock (phi2) external clock (eclk/pc2) output port (if write to output port)
freescale 4-4 mc68HC05B6 rev. 4.1 input/output ports 4 a digital read of port d wit h levels other than v dd or v ss on the port d pins will result in greater power dissipation duri ng the read cycle. as port d is an input-only port there is no ddr associated with it. also, at power up or external reset, the a/d converter is disabled, thus the po rt is configured as a standard input-only port. note: it is recommended that all unused input ports and i/o ports be tied to an appropriate logic level (i.e. either v dd or v ss ). 4.5 port registers the following sections explain in detail the indi vidual bits in the data and control registers associated with the ports. 4.5.1 port data registers a and b (porta and portb) each bit can be configured as input or output vi a the corresponding data direction bit in the port data direction register (ddrx). the state of the port data registers following reset is not defined. 4.5.2 port data register c (portc) each bit can be configured as input or output vi a the corresponding data direction bit in the port data direction register (ddrx). in addition, bit 2 of port c is used to outp ut the cpu clock if the eclk bit in the eeprom ctl/eclk register is set (see section 4.3 ). the state of the port data registers following reset is not defined. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 undefined port b data (portb) $0001 undefined address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port c data (portc) $0002 pc2/ eclk undefined
mc68HC05B6 rev. 4.1 freescale 4-5 input/output ports 4 4.5.3 port data register d (portd) all the port d bits are input-only and are shared with the a/d converter. the function of each bit is determined by the adon bit in t he a/d status/control register. the state of the port data registers following reset is not defined. 4.5.3.1 a/d status /control register adon ? a/d converter on 1 (set) ? a/d converter is switched on; all port d pins act as analog inputs for the a/d converter. 0 (clear) ? a/d converter is switched off; all port d pins act as input only pins. reset clears the adon bit, thus configuring port d as an input only port. 4.5.4 data direction regist ers (ddra, ddr b and ddrc) writing a ?1? to any bit configures the corresponding port pin as an output; conversely, writing any bit to ?0? configures the corresponding port pin as an input. reset clears these registers, thus configuring all ports as inputs. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 undefined address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset a/d status/control $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000
freescale 4-6 mc68HC05B6 rev. 4.1 input/output ports 4 4.6 other port considerations all output ports can emulate ?open-drain? outputs. this is achieved by writing a zero to the relevant output port latch. by toggling the corresponding da ta direction bit, the port pin will either be an output zero or tri-state (an input). this is shown diagrammatically in figure 4-3 . when using a port pin as an ?open-drain? output, certain precautions must be taken in the user software. if a read-modify-write instruction is used on a port where the ?open-drain? is assigned and the pin at this time is programmed as an inpu t, it will read it as a ?one?. the read-modify-write instruction will then write this ?o ne? into the output dat a latch on the next cycle. this would cause the ?open-drain? pin not to output a ?zero? when desired. note: ?open-drain? outputs should not be pulled above v dd . figure 4-3 port logic levels ddrn a y (b) 100 normal operation ? tri state 111 00tri state 01tri state 10low ?open-drain? 11? 0 0 high 0 1 high ? ? ? ? ? ? ? ? ? ? y a read buffer output data direction register bit ddrn px0 vdd v dd ddrx, bit 0 = 0 portx, bit 0 = 0 ddrx, bit 0 = 0 portx, bit 0 = 0 (c) (a) ?open-drain? output
mc68HC05B6 rev. 4.1 freescale 5-1 programmable timer 5 5 programmable timer the programmable timer on the mc68HC05B6 consists of a 16-bit read-only free-running counter, with a fixed divide-by-four prescaler, plus the in put capture/output compare circuitry. the timer can be used for many purposes including measuring pulse length of two input signals and generating two output signals. pulse lengths for both input and output signals can vary from several microseconds to many seconds. in addition, it works in conjunction with the pulse length modulation (plm) system, which can also be re ferred to as the pulse width modulation system, to execute two 8-bit d/a plm (pulse length modulation) conversions, with a choice of two repetition rates. the timer is also capable of generating periodic interrupts or indicating passage of an arbitrary multiple of four cpu cycles. a block diagram is shown in figure 5-1 , and timing diagrams are shown in figure 5-2 , figure 5-3 , figure 5-4 and figure 5-5 . the timer has a 16-bit architecture, hence each spec ific functional segment is represented by two 8-bit registers (except the plma and plmb which us e one 8-bit register for each). these registers contain the high and low byte of that functional s egment. accessing the low byte of a specific timer function allows full control of that function; howeve r, an access of the high byte inhibits that specific timer function until the low byte is also accessed. the 16-bit programmable timer is monitored and controlled by a group of sixteen registers, full details of which are contained in this section. note: a problem may arise if an interrupt occurs in the time between the high and low bytes being accessed. to prevent this, the i-bit in the condition code register (ccr) should be set while manipulating both the high and low byte register of a specific timer function, ensuring that an interrupt does not occur. 5.1 counter the key element in the programmable timer is a 16- bit, free-running counter or counter register, preceded by a prescaler that divides the internal processor clock by four. the prescaler gives the timer a resolution of 2 s if the internal bus clock is 2 mhz. the counter is incremented during the low portion of the internal bus clock. software can read the counter at any time without affecting its value.
freescale 5-2 mc68HC05B6 rev. 4.1 programmable timer 5 figure 5-1 16-bit programmable timer block diagram internal internal bus 8 output compare register 1 processor clock + + 8-bit buffer 4 high low 16-bit free-running counter counter alternate register register 1 register 2 input capture internal timer bus overflow detect circuit edge detect tcap1 tcmp2 tcmp1 latch d c q compare output register 2 input capture byte byte high byte low byte high byte low byte high byte low byte low byte high byte circuit 1 compare output circuit 2 compare output circuit 1 edge detect circuit 2 tcap2 pin pin pin pin d c q latch 76543 timer status register timer control $0013 $0012 $0018 $0019 $001a $001b $001c $0016 $0017 $0014 $0015 $001e $001f $001d to plm register icf1 ocf1 tof icf2 ocf2 icie ocie toie folv2 olvl2 iedg1 olvl1 folv1 interrupt circuit input capture interrupt $1ff8,9 output compare interrupt $1ff6,7 overflow interrupt $1ff4,5 cop watchdog counter input
mc68HC05B6 rev. 4.1 freescale 5-3 programmable timer 5 5.1.1 counter register and alternate counter register the double-byte, free-running counter can be read from either of two locations, $18-$19 (counter register) or $1a-$1b (alternate c ounter register). a read from only the less significant byte (lsb) of the free-running counter ($19 or $1b) receives the count value at the ti me of the read. if a read of the free-running counter or alternate counter register first addresses the more significant byte (msb) ($18 or $1a), the lsb is transferred to a buff er. this buffer value remains fixed after the first msb read, even if the user reads the msb severa l times. this buffer is accessed when reading the free-running counter or alternate counter regi ster lsb and thus completes a read sequence of the total counter value. in reading either the free-running counter or al ternate counter register, if the msb is read, the lsb must also be read to complete the sequence. if the timer overflow flag (tof) is set when the counter regi ster lsb is read then a read of the timer status register (tsr) will clear the flag. the alternate counter register differs from the co unter register only in that a read of the lsb does not clear tof. therefore, where it is critical to avoid the possibility of missing timer overflow interrupts due to clearing of tof, the alternate counter register should be used. the free-running counter is set to $fffc during power-on and external reset and is always a read-only register. during a power-on reset, the counter begins running after the oscillator start-up delay. because the free-running counter is 16 bits preceded by a fixed divide-by-4 prescaler, the value in the free-running counter repeats every 262,144 internal bus cloc k cycles. tof is set when the counter overflows (from $ffff to $0000); this will cause an interrupt if toie is set. in some particular timing control applications it may be desirable to reset the 16-bit free running counter under software control. when the low byte of the counter ($19 or $1b) is written to, the counter is configured to its reset value ($fffc). the divide-by-4 prescaler is also reset and the counter resumes normal counting operation. all of the flags and enable bits remain unaltered by th is operation. if access has previously been made to the high byte of the free-running counter ($18 or $1a), then the reset counter operation terminates the access sequence. warning: this operation may affect the func tion of the watchdog system (see section 9.1.4 ). the plm results will also be affected while resetting the counter. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100
freescale 5-4 mc68HC05B6 rev. 4.1 programmable timer 5 5.2 timer control and status the various functions of the timer are monitore d and controlled using the timer control and status registers described below. 5.2.1 timer control register (tcr) the timer control register ($0012) is used to enable the input captures (icie), output compares (ocie), and timer overflow (toie) functions as well as forcing output compares (folv1 and folv2), selecting input edge sensitivity (iedg1) and levels of output polarity (olv1 and olv2). icie ? input captures interrupt enable if this bit is set, a timer interrupt is enabled wh enever the icf1 or icf2 status flag (in the timer status register) is set. 1 (set) ? interrupt enabled. 0 (clear) ? interrupt disabled. ocie ? output compares interrupt enable if this bit is set, a timer interrupt is enabled w henever the ocf1 or ocf2 status flag (in the timer status register) is set. 1 (set) ? interrupt enabled. 0 (clear) ? interrupt disabled. toie ? timer overflow interrupt enable if this bit is set, a timer interrupt is enabled whenever the tof status flag (in the timer status register) is set. 1 (set) ? interrupt enabled. 0 (clear) ? interrupt disabled. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0
mc68HC05B6 rev. 4.1 freescale 5-5 programmable timer 5 folv2 ? force output compare 2 this bit always reads as zero, hence writing a zero to this bit has no effect. writing a one at this position will force the olv2 bit to the corresponding output level latch, thus appearing at the tcmp2 pin. note that this bit does not affect the oc f2 bit of the status register (see section 5.4.3 ). 1 (set) ? olv2 bit forced to output level latch. 0 (clear) ? no effect. folv1 ? force output compare 1 this bit always reads as zero, hence writing a zero to this bit has no effect. writing a one at this position will force the olv1 bit to the corresponding output level latch, thus appearing at the tcmp1 pin. note that this bit does not affect the oc f1 bit of the status register (see section 5.4.3 ). 1 (set) ? olv1 bit forced to output level latch. 0 (clear) ? no effect. olv2 ? output level 2 when olv2 is set a high output level will be clocked into the output level register by the next successful output compare, and will appear on the tcmp2 pin. when clear, it will be a low level which will appear on the tcmp2 pin. 1 (set) ? a high output level will appear on the tcmp2 pin. 0 (clear) ? a low output level will appear on the tcmp2 pin. iedg1 ? input edge 1 when iedg1 is set, a positive-going edge on the tcap1 pin will trigger a transfer of the free-running counter value to the input captur e register 1. when clear, a negative-going edge triggers the transfer. 1 (set) ? tcap1 is positive-going edge sensitive. 0 (clear) ? tcap1 is negative-going edge sensitive. note: there is no need for an equivalent bit for the input capture register 2 as tcap2 is negative-going edge sensitive only. olv1 ? output level 1 when olv1 is set a high output level will be clocked into the output level register by the next successful output compare, and will appear on the tcmp1 pin. when clear, it will be a low level which will appear on the tcmp1 pin. 1 (set) ? a high output level will appear on the tcmp1 pin. 0 (clear) ? a low output level will appear on the tcmp1 pin.
freescale 5-6 mc68HC05B6 rev. 4.1 programmable timer 5 5.2.2 timer status register (tsr) the timer status register ($13) is a read only re gister and contains the status bits corresponding to the four timer interrupt conditions ? icf1,ocf1, tof, icf2 and ocf2. accessing the timer status register satisfies the first condition requir ed to clear the status bits. the remaining step is to access the regist er corresponding to the status bit. icf1 ? input capture flag 1 this bit is set when the selected polarity of edg e is detected by the input capture edge detector 1 at tcap1; an input capture interrupt will be generated, if icie is set. icf1 is cleared by reading the tsr and then the input capture low register 1 ($15). 1 (set) ? a valid input capture has occurred. 0 (clear) ? no input capture has occurred. ocf1 ? output compare flag 1 this bit is set when the output compare 1 regi ster contents match t hose of the free-running counter; an output compare interrupt will be generated if ocie is set. ocf1 is cleared by reading the tsr and then reading or writing the output compare 1 low register ($17). 1 (set) ? a valid output compare has occurred. 0 (clear) ? no output compare has occurred. tof ? timer overflow status flag this bit is set when the free-running counter overflows from $ffff to $0000; a timer overflow interrupt will occur if toie is set. tof is cleared by reading the tsr and the count er low register ($19). 1 (set) ? timer overflow has occurred. 0 (clear) ? no timer overflow has occurred. when using the timer overflow function and reading the free-running counter at random times to measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally cleared if: 1 the timer status register is read or written when tof is set, and 1) the lsb of the free-running counter is read, but not for the purpose of servicing the flag. reading the alternate counter register instead of the counter register will avoid this potential problem. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 undefined
mc68HC05B6 rev. 4.1 freescale 5-7 programmable timer 5 icf2 ? input capture flag 2 this bit is set when a negative edge is detected by the input capture edge detector 2 at tcap2; an input capture interrupt will be generated if icie is set. icf2 is cleared by reading the tsr and then the input capture low register 2 ($1d). 1 (set) ? a valid (negative) input capture has occurred. 0 (clear) ? no input capture has occurred. ocf2 ? output compare flag 2 this bit is set when the output compare 2 regist er contents match those of the free-running counter; an output compare interrupt will be generat ed if ocie is set. ocf2 is cleared by reading the tsr and then reading or writing the output compare 2 lo w register ($1f). 1 (set) ? a valid output compare has occurred. 0 (clear) ? no output compare has occurred. 5.3 input capture ?input capture? is a technique whereby an external signal is used to trigger a read of the free running counter. in this way it is possible to relate the timing of an external signal to the internal counter value, and hence to elapsed time. there are two input capture registers: input capture register 1 (icr1) and input capture register 2 (icr2). the same input capture interrupt enable bit (icie) is used for the two input captures. 5.3.1 input capture register 1 (icr1) the two 8-bit registers that make up the 16-bit in put capture register 1 are read-only, and are used to latch the value of the free-running counter afte r the input capture edge detector circuit 1 senses a valid transition at tcap1. the level transition that triggers the counter transfer is defined by the input edge bit (iedg1). when an input capture 1 occurs, the corresponding flag icf1 in tsr is set. an interrupt can also accompany an input capture 1 provided the icie bit in tcr is set. the 8 most significant bits are stored in the input capture high 1 register at $14, the 8 least significant bits in the input capture low 1 register at $15. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset input capture high 1 $0014 undefined input capture low 1 $0015 undefined
freescale 5-8 mc68HC05B6 rev. 4.1 programmable timer 5 the result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus cloc k preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are tr ansferred to the input capture register 1 on each valid signal transition whether the input capture 1 flag (icf1) is set or clear. the input capture register 1 always contains the free-running counter value that corresponds to the most recent input capture 1. after a read of the input capture 1 register msb ($14), the counter transfer is inhibited until the l sb ($15) is also read. this characteristic causes the time used in the input capture software rout ine and its interaction with the main program to determine the minimum pulse period. a read of th e input capture 1 register lsb ($15) does not inhibit the free-running counter transfer since the two actions occur on opposite edges of the internal bus clock. reset does not affect the contents of the input capture 1 register, except when exiting stop mode (see section 5.6 ). 5.3.2 input capture r egister 2 (icr2) the two 8-bit registers that make up the 16-bit i nput capture register 2 are read-only, and are used to latch the value of the free-running counter afte r the input capture edge detector circuit 2 senses a negative transition at pin tcap2. when an input capture 2 occurs, the corresponding flag icf2 in tsr is set. an interrupt can also accompany an input capture 2 provided the icie bit in tcr is set.the 8 most significant bits are stored in the input capture 2 high regi ster at $1c, the 8 least significant bits in the input capture 2 low register at $1d. the result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus cloc k preceding the external transition. this delay is required for internal synchronization. resolution is one count of the free-running counter, which is four internal bus clock cycles. the free-running counter contents are tr ansferred to the input capture register 2 on each negative signal transiti on whether the input captur e 2 flag (ic2f) is set or clear. the input capture register 2 always contains the free-running counter value that corresponds to the most recent input capture 2. after a read of the input capture register 2 msb ($1c), the counter transfer is inhi bited until the lsb ($1d) is also read. this characteristic causes the time used in the input capture software rout ine and its interaction with the main program to determine the minimum pulse period. a read of t he input capture register 2 lsb ($1c) does not inhibit the free-running counter transfer since the two actions occur on opposite edges of the internal bus clock. reset does not affect the contents of the input capture 2 register, except when exiting stop mode (see section 5.6 ). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset input capture high 2 $001c undefined input capture low 2 $001d undefined
mc68HC05B6 rev. 4.1 freescale 5-9 programmable timer 5 5.4 output compare ?output compare? is a technique which may be used, for example, to generate an output waveform, or to signal when a specific time period has elapsed, by presetting the output compare register to the appropriate value. there are two output co mpare registers: outpu t compare register 1 (ocr1) and output compare register 2 (ocr2), both of which are read or write registers. note: the same output compare interrupt enable bit (ocie) is used for the two output compares. 5.4.1 output compare register 1 (ocr1) the 16-bit output compare re gister 1 is made up of two 8-bit registers at locations $16 (msb) and $17 (lsb). the contents of the out put compare register 1 are compared with the contents of the free-running counter continually and, if a matc h is found, the corresponding output compare flag (ocf1) in the timer status register is set and t he output level (olvl1) is transferred to pin tcmp1. the output compare register 1 values and the output level bit should be changed after each successful comparison to establish a new elapsed timeout. an interrupt can also accompany a successful output compare provided the corresp onding interrupt enable bit (ocie) is set. (the free-running counter is updated every four internal bus clock cycles.) after a processor write cycle to the output compar e register 1 containing the msb ($16), the output compare function is inhibited until the lsb ($17) is also written. the user must write both bytes (locations) if the msb is written first. a write made only to the lsb ($17) will not inhibit the compare 1 function. the processor can write to either byte of the output compare regi ster 1 without affecting the other byte. the output level (olvl1) bit is clocke d to the output level register and hence to the tcmp1 pin whether the output compare flag 1 (ocf 1) is set or clear. the minimum time required to update the output compare register 1 is a function of the program rather than the internal hardware. because the output compare flag 1 and the output compare regi ster 1 are not defined at power on, and not affected by reset, care must be taken when initializing output compare functions with software. the following procedure is recommended: ? write to output compare high 1 to inhibit further compares; ? read the timer status register to clear ocf1 (if set); ? write to output compare low 1 to enable the output compare 1 function. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset output compare high 1 $0016 undefined output compare low 1 $0017 undefined
freescale 5-10 mc68HC05B6 rev. 4.1 programmable timer 5 the purpose of this procedure is to prevent the ocf1 bit from being set between the time it is read and the write to the correspondi ng output compare register. all bits of the output compare re gister are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. 5.4.2 output compare register 2 (ocr2) the 16-bit output compare register 2 is made up of two 8-bit registers at locations $1e (msb) and $1f (lsb). the contents of the ou tput compare register 2 are co mpared with the contents of the free-running counter continually and, if a match is found, the corresponding output compare flag (ocf2) in the timer status register is set and the output level (olvl2) is transferred to pin tcmp2. the output compare regi ster 2 values and the output level bit should be changed after each successful comparison to establ ish a new elapsed timeout. an interrupt can also accompany a successful output compare provided the corresponding interrupt enable bit (ocie) is set. (the free-running counter is updated every four internal bus clock cycles.) after a processor write cycle to the output compare register 2 co ntaining the msb ($1e), the output compare function is inhibi ted until the lsb ($1f) is also written. the user must write both bytes (locations) if the msb is written first. a wr ite made only to the lsb ($1f) will not inhibit the compare 2 function. the processor can write to either byte of the output compare register 2 without affecting the other byte. the out put level (olvl2) bit is clocked to the output level register and hence to the tcmp2 pin whether the output com pare flag 2 (ocf2) is set or clear. the minimum time required to update the output compare register 2 is a function of the program rather than the internal hardware. because the output compare flag 2 and the output compare register 2 are not defined at power on, and not affected by reset, care must be taken when initializing output compare functions with software. the following procedure is recommended: ? write to output compare high 2 to inhibit further compares; ? read the timer status register to clear ocf2 (if set); ? write to output compare low 2 to enable the output compare 2 function. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset output compare high 2 $001e undefined output compare low 2 $001f undefined
mc68HC05B6 rev. 4.1 freescale 5-11 programmable timer 5 the purpose of this procedure is to prevent the ocf1 bit from being set between the time it is read and the write to the correspo nding output compare register. all bits of the output compare re gister are readable and writable and are not altered by the timer hardware or reset. if the compare function is not needed, the two bytes of the output compare register can be used as storage locations. 5.4.3 software force compare a software force compare is required in many applications. to achieve this, bit 3 (folv1 for ocr1) and bit 4 (folv2 for ocr2) in the timer control register are used. these bits always read as ?zero?, but a write to ?one? causes the respective olvl1 or olvl2 values to be copied to the respective output level (tcmp1 and tcmp2 pins). internal logic is arranged such that in a single instruction, one can change olvl1 and/or olvl2, at the same time causing a forced output comp are with the new values of olvl1 and olvl2. in conjunction with normal compare, this function a llows a wide range of applications including fixed frequency generation. note: a software force compare will affect the corresponding output pin tcmp1 and/or tcmp2, but will not affect the compare fl ag, thus it will not generate an interrupt. 5.5 pulse length modulation (plm) the programmable timer works in conjunction with the plm system to execute two 8-bit d/a plm conversions, with a choice of two repetition rates (see section 7 ). 5.5.1 pulse length modulation r egisters a and b (plma/plmb) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset pulse length modulation a (plma) $000a 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset pulse length modulation b (plmb) $000b 0000 0000
freescale 5-12 mc68HC05B6 rev. 4.1 programmable timer 5 5.6 timer during stop mode when the mcu enters stop mode, the timer counter stops counting and remains at that particular count value until stop mode is exited by an interrupt. if stop mode is exited by power-on or external reset, the counter is forced to $fffc but if it is exited by external interrupt (irq ) then the counter resumes from its stopped value. another feature of the programmabl e timer is that if at least one valid input capture edge occurs at one of the tcap pins while in stop mode, the corresponding input capture detect circuitry is armed. this action does not wake the mcu or set any timer flags, but when the mcu does wake-up there will be an active input capture flag (and data) from that first valid edge which occurred during stop mode. if stop mode is exited by an external reset then no such input capture flag or data action takes place even if there was a valid input capture edge (at one of the tcap pins) during stop mode. 5.7 timer during wait mode the timer system is not affected by wait mode and continues no rmal operation. any valid timer interrupt will wake-up the system. 5.8 timer state diagrams the relationships between the internal clock sign als, the counter contents and the status of the flag bits are shown in the following figures. it s hould be noted that the signals labelled ?internal? (processor clock, timer clocks and reset) are not available to the user.
mc68HC05B6 rev. 4.1 freescale 5-13 programmable timer 5 figure 5-2 timer state timing diagram for reset figure 5-3 timer state timing diagram for input capture internal processor clock internal reset 16-bit counter external reset or end of por internal timer clocks ? ? ? ? ? $fffc $fffd $fffe $ffff note: the counter and timer control registers are the only ones affected by power-on or external reset. t00 t01 t11 t10 internal processor clock 16-bit counter $f123 $f124 $f125 $f126 internal timer clocks ? ? ? ? ? t00 t01 t11 t10 internal capture latch $f124 $???? input capture register input capture flag input edge } } } } note: if the input edge occurs in the shaded area from one timer state t10 to the next timer state t10, then the input capture flag will be set during the next t11 state.
freescale 5-14 mc68HC05B6 rev. 4.1 programmable timer 5 figure 5-4 timer state timing diagram for output compare figure 5-5 timer state timing diag ram for timer overflow internal processor clock 16-bit counter $f456 $f457 $f458 $f459 internal timer clocks ? ? ? ? ? t00 t01 t11 t10 $f457 cpu writes $f457 output compare flag and tcmp1,2 note: 1 the cpu write to the compare registers may take plac e at any time, but a compare only occurs at timer state t01. thus a four cycle difference may exist between the wr ite to the compare register and the actual compare. 1) the output compare flag is set at the timer state t11 that follows the comparison match ($f457 in this example). output compare register compare register latch (note 2) (note 1) (note 1) internal processor clock 16-bit counter $ffff $0000 $0001 $0002 internal timer clocks ? ? ? ? ? t00 t01 t11 t10 note: the timer overflow flag is set at timer state t11 (transition of counter from $ffff to $0000). it is cleared by a read of the timer status regist er during the internal pr ocessor clock high time, followed by a read of the counter low register. timer overflow flag
mc68HC05B6 rev. 4.1 freescale 6-1 serial communications interface 6 6 serial communications interface a full-duplex asynchronous serial communicati ons interface (sci) is provided with a standard non-return-to-zero (nrz) format and a variety of baud rates. the sci transmitter and receiver are functionally independent and have their own baud rate generator; however they share a common baud rate prescaler and data format. the serial data format is standard mark/space (nrz) and provides one start bit, eight or nine data bits, and one stop bit. the sclk pin is the output of the transmitter clock. it outputs the transmitter data clock for synchronous transmission (no clocks on start bit and stop bit, and a software option to send clock on last data bit). this allows control of peripher als containing shift registers (e.g. lcd drivers). phase and polarity of these clocks are software programmable. any sci bidirectional communication requires a two-wire system: rece ive data in (rdi) and transmit data out (tdo). ?baud? and ?bit rate? are used synonymously in the following description. 6.1 sci two-wire system features standard nrz (mark/space) format advanced error detection method with noise detecti on for noise duration of up to 1/16th bit time full-duplex operation (simultaneous transmit and receive) 32 software selectable baud rates different baud rates for transmit and receive; for each transmit baud rate, 8 possible receive baud rates software selectable word length (eight or nine bits) separate transmitter and receiver enable bits capable of being interrupt driven transmitter clocks available without altering t he regular transmitter or receiver functions four separate enable bits for interrupt control 71
freescale 6-2 mc68HC05B6 rev. 4.1 serial communications interface 6 figure 6-1 serial communications interface block diagram & & & & + + internal bus sci interrupt transmit receive tdo pin rdi transmitter control receiver control clock clock extraction phase and polarity control pin receiver clock transmitter flag control data register data register tie tcie rie ilie te re sbk rwu 7 6 5 4 3 2 1 0 $000f sccr2 scsr $0010 sccr1 $000e trde tc rdrf idle or nf fe te sbk $0011 (see note) (see note) r8 t8 m wake cpol cpha lbcl 0 1 2 4 3 6 5 7 765 2 3 4 1 sclk pin wake up unit receive data shift register transmit data shift register $0011 note: the serial communications da ta register (sci scdr) is controlled by the internal r/w signal. it is the transmit data register when written to and the receive data register when read. 7 71
mc68HC05B6 rev. 4.1 freescale 6-3 serial communications interface 6 6.2 sci receiver features receiver wake-up function (idle line or address bit) idle line detection framing error detection noise detection overrun detection receiver data register full flag 6.3 sci transmitter features transmit data register empty flag transmit complete flag send break 6.4 functional description a block diagram of the sci is shown in figure 6-1 . option bits in serial control register1 (sccr1) select the ?wake-up? method (wake bit) and data word length (m-bit) of the sci. sccr2 provides control bits that individually enable the tr ansmitter and receiver, e nable system interrupts and provide the wake-up enable bit (rwu) and the send break code bit (sbk). control bits in the baud rate register (baud) allow the us er to select one of 32 different baud rates for the transmitter and receiver (see section 6.11.5 ). data transmission is initiated by writing to t he serial communications data register (scdr). provided the transmitter is enabled, data stored in the scdr is transferred to the transmit data shift register. this transfer of data sets the tr ansmit data register empty flag (tdre) in the sci status register (scsr) and generates an inte rrupt (if transmitter interrupts are enabled). the transfer of data to the transmit data shift regi ster is synchronized with the bit rate clock (see figure 6-2 ). all data is transmitted least significant bi t first. upon completion of data transmission, the transmission complete flag (tc) in the scsr is set (provided no pending data, preamble or break is to be sent) and an interrupt is generated (if the transmit complete interrupt is enabled). if the transmitter is disabled, and the data, preamble or break (in the transmit data shift register) has been sent, the tc bit will also be set. this will also generate an interrupt if the transmission complete interrupt enable bit (tcie) is set. if the transmitter is di sabled during a transmission, the character being transmitted will be completed before the transmitter gives up control of the tdo pin. 71
freescale 6-4 mc68HC05B6 rev. 4.1 serial communications interface 6 when scdr is read, it contains th e last data byte received, provid ed that the receiver is enabled. the receive data register full flag bit (rdrf) in the scsr is set to indicate that a data byte has been transferred from the input serial shift regist er to the scdr; this will cause an interrupt if the receiver interrupt is enabled. the data transfer fr om the input serial shift register to the scdr is synchronized by the receiver bit rate clock. the or (overrun), nf (noise), or fe (framing) error flags in the scsr may be set if data reception errors occurred. an idle line interrupt is generated if the idle line interrupt is enabled and the idle bit (which detects idle line transmission) in scsr is set. this allows a receiver that is not in the wake-up mode to detect the end of a message or the preamble of a new message, or to resynchronize with the transmitter. a valid character must be received befor e the idle line condition or the idle bit will not be set and idle line interrupt will not be generated. the scp0 and scp1 bits function as a prescaler for scr0?scr2 to generate the receiver baud rate and for sct0?sct2 to generate the transmitter baud rate. together, these eight bits provide multiple transmitter/receiver rate combinations for a given crystal frequency (see figure 6-2 ). this register should only be written to while both the transmi tter and receiver are disabled (te=0, re=0). figure 6-2 sci rate generator division scp1 spc0 sct2 sct1 sct0 scr2 scr1 scr0 internal processor clock scp0 ? scp1 prescaler rate control ( np) scr0 ? scr2 receiver ( nr) sct0 ? sct2 transmitter rate control ( nt) 16 transmitter clock receiver clock rate control 76543210 $000d baud rate register note: there is a fixed rate divide-by-16 before the transmitter to com pensate for the inherent divide-by- 16 of the receiver (sampling ). this means that by loading the same value for both the trans mitter and receiver baud rate selector, the same baud rates can be obtained. 71
mc68HC05B6 rev. 4.1 freescale 6-5 serial communications interface 6 6.5 data format receive data or transmit data is the serial data that is transferred to the internal data bus from the receive data input pin (rdi) or from the internal bus to the transmit data output pin (tdo). the non-return-to-zero (nrz) data format shown in figure 6-3 is used and must meet the following criteria: ? the idle line is brought to a logic one state prior to transmission/reception of a character. ? a start bit (logic zero) is used to indicate the start of a frame. ? the data is transmitted and received least significant bit first. ? a stop bit (logic one) is used to indicate the end of a frame. a frame consists of a start bit, a character of eight or nine data bits, and a stop bit. ? a break is defined as the transmission or reception of a low (logic zero) for at least one complete frame time (10 zeros for 8-bit format, 11 zeros for 9-bit). 6.6 receiver wake-up operation the receiver logic hardware also supports a receiver wake-up function which is intended for systems having more than one receiver. with this function a transmitting device directs messages to an individual receiver or group of receivers by passing addressing information as the initial byte(s) of each message. the wake-up function allows receivers not addressed to remain in a dormant state for the remainder of the unwanted message. this eliminates any further software overhead to service the remaining characters of the unwanted mess age and thus improves system performance. the receiver is placed in wake-up mode by setting the receiver wake-up bit (rwu) in the sccr2 register. while rwu is set, all of the receiver related status flags (rdrf, idle, or, nf, and fe) are inhibited (cannot become set). note that the idle line detect function is inhibited while the rwu bit is set. although rwu may be cleared by a software write to sccr2, it would be unusual to do so. normally rwu is set by software and is clear ed automatically in hardware by one of the two methods described below. figure 6-3 data format start stop control bit m selects 8 or 9 bit data start idle line 012345678 ? ? ? 0 71
freescale 6-6 mc68HC05B6 rev. 4.1 serial communications interface 6 6.6.1 idle line wake-up in idle line wake-up mode, a dormant receiver wakes up as soon as the rdi line becomes idle. idle is defined as a continuous logic high level on the rdi line for ten (or eleven) full bit times. systems using this type of wake-up must provid e at least one character time of idle between messages to wake up sleeping receivers, but must not allow any idle time between characters within a message. 6.6.2 address mark wake-up in address mark wake-up, the most significant bit (m sb) in a character is used to indicate whether it is an address (1) or data (0) character. sleeping receivers will wake up whenever an address character is received. systems using this met hod for wake-up would set the msb of the first character of each message and leave it clear for all other characters in the message. idle periods may be present within messages and no idle time is required between messages for this wake-up method. 6.7 receive data in (rdi) receive data is the serial data that is applied th rough the input line and the sci to the internal bus. the receiver circuitry clocks the input at a rate equal to 16 times the baud rate. this time is referred to as the rt rate in figure 6-4 and as the receiver clock in figure 6-2 . the receiver clock generator is controlled by the baud rate register, as shown in figure 6-1 and figure 6-2 ; however, the sci is synchronized by the start bit, independent of the transmitter. once a valid start bit is detected, the start bit, each data bit and the stop bit are sampled three times at rt intervals 8 rt, 9 rt and 10 rt (1 rt is the position where the bi t is expected to start), as shown in figure 6-5 . the value of the bit is determined by voting logic which takes the value of the majority of the samples. a noise flag is set when all three samples on a valid start bit or data bit or the stop bit do not agree. 6.8 start bit detection when the input (idle) line is detec ted low, it is tested for three more sample times (referred to as the start edge verification samples in figure 6-4 ). if at least two of these three verification samples detect a logic zero, a valid start bit has been detected, otherwise the line is assumed to be idle. a noise flag is set if one of the three verification samples detect a logic one, thus a valid start bit could be assumed with a set noise flag present. 71
mc68HC05B6 rev. 4.1 freescale 6-7 serial communications interface 6 if there has been a framing error without detection of a break (10 zeros for 8 bit format or 11 zeros for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the start edge will be placed artificially. the last bit received in the data shift register is inverted to a logic one, and the three logic one start qualifiers (shown in figure 6-4 ) are forced into the sample shift register during the interval when detect ion of a start bit is anticipated (see figure 6-6 ); therefore, the start bit will be accepted no sooner than it is anticipated. figure 6-4 sci examples of start bit sampling technique figure 6-5 sci sampling technique used on all bits 111 1 11 1 1 1 11 0000 1rt 2rt 3rt 5rt 7rt 4rt 6rt 8rt start qualifiers idle start edge verification samples 16x internal sampling clock rt clock edges for all three examples noise start 111 1 11 1 1 1 0 1 0000 111 1 11 1 1 1 1 1 0010 start start noise rdi rdi rdi < < < samples present bit next bit previous bit 16rt 1rt 8rt 9rt 10rt 16rt 1rt rdi 71
freescale 6-8 mc68HC05B6 rev. 4.1 serial communications interface 6 if the receiver detects that a break (rdrf = 1, fe = 1, receiv er data register = $0000) produced the framing error, the start bit will not be artificial ly induced and the receiv er must actually detect a logic one before the start bit can be recognised (see figure 6-7 ). 6.9 transmit data out (tdo) transmit data is the serial data from the internal data bus that is applied through the sci to the output line. data format is as discussed in section 6.5 and shown in figure 6-3 . the transmitter generates a bit time by using a derivative of the rt clock, thus producing a transmission rate equal to 1/16th that of the receiver sample clock (assuming the same baud rate is selected for both the receiver and transmitter). figure 6-6 artificial start following a framing error figure 6-7 sci start bit following a break data expected stop data samples artificial edge start bit data rdi data expected stop data samples start edge start bit data rdi a) case 1: receive line low during artificial edge b) case 2: receive line hi gh during expected start edge expected stop data samples detected as valid start edge start bit rdi break ? ? ? ? ? ? ? ? ? ? ? ? ? start qualifiers start edge verification samples 71
mc68HC05B6 rev. 4.1 freescale 6-9 serial communications interface 6 6.10 sci synchronous transmission the sci transmitter allows the user to control a one way synchronous serial transmission. the sclk pin is the clock output of the sci transmitter. no clocks are sent to that pin during start bit and stop bit. depending on the state of the lbcl bit (bit 0 of sccr1), clocks will or will not be activated during the last valid data bit (address mark). the cpol bit (bit 2 of sccr1) allows the user to select the clock polarity, and the cpha bi t (bit 1 of sccr1) allows the user to select the phase of the external clock (see figure 6-8 , figure 6-9 and figure 6-10 ). during idle, preamble and send break, the external sclk clock is not activated. these options allow the user to serially control pe ripherals which consist of shift registers, without losing any functions of the sci transmitter which ca n still talk to other sci receivers. these options do not affect the sci receiver which is independent of the transmitter. the sclk pin works in conjunction with the tdo pin. when the sci transmitter is disabled (te = 0), the sclk and tdo pins go to the high impedance state. note: the lbcl, cpol and cpha bits have to be selected before enabling the transmitter to ensure that the clocks function correctly. these bits should not be changed while the transmitter is enabled. figure 6-8 sci example of synchronous and asynchronous transmission rdi tdo sclk output port data out data in data in clock enable asynchronous mc68HC05B6 (e.g. modem) synchronous (e.g. shift register, display driver, etc.) 71
freescale 6-10 mc68HC05B6 rev. 4.1 serial communications interface 6 6.11 sci registers the sci system is configured and controlled by five registers: scdr, sccr1, sccr2, scsr, and baud. 6.11.1 serial communicati ons data register (scdr) the scdr is controlled by the internal r/w signal and performs two functions in the sci. it acts as the receive data register (rdr) when it is re ad and as the transmit data register (tdr) when it is written. figure 6-1 shows this register as two separ ate registers, rdr and tdr. the rdr provides the interface from the receive shift regi ster to the internal data bus and the tdr provides the parallel interface from the internal data bus to the transmit shift register. the receive data register is a read-only register co ntaining the last byte of data received from the shift register for the internal data bus. the rdr fu ll bit (rdrf) in the serial communications status register is set to indicate that a byte has been tran sferred from the input serial shift register to the scdr. the transfer is synchronized with the receiver bit rate clock (from the receiver control) as shown in figure 6-1 . all data is received with the least significant bit first. the transmit data register (tdr) is a write-only register containing the next byte of data to be applied to the transmit shift register from the in ternal data bus. as long as the transmitter is enabled, data stored in the scdr is transferred to the transmit shift register (after the current byte in the shift register has been transmitted). the transfer is synchronized with the transmitter bit rate clock (from the transmitter control) as shown in figure 6-1 . all data is received with the least significant bit first. 6.11.2 serial communications control register 1 (sccr1) the sci control register 1 (sccr1) contains contro l bits related to the nine data bit character format, the receiver wake-up feature and the options to output the transmitter clocks for synchronous transmissions. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset sci data (scdr) $0011 0000 0000 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl undefined 71
mc68HC05B6 rev. 4.1 freescale 6-11 serial communications interface 6 r8 ? receive data bit 8 this read-only bit is the ninth se rial data bit received when the sci system is configured for nine data bit operation (m = 1). the most significant bi t (bit 8) of the received character is transferred into this bit at the same time as the remaining eight bits (bits 0?7) are transferred from the serial receive shifter to the sci receive data register. t8 ? transmit data bit 8 this read/write bit is the ninth data bit to be tr ansmitted when the sci system is configured for nine data bit operation (m = 1). when the eight low or der bits (bits 0?7) of a transmit character are transferred from the sci data register to the se rial transmit shift regist er, this bit (bit 8) is transferred to the ninth bit position of the shifter. m ? mode (select character format) the read/write m-bit controls the character length for both the transmitter and receiver at the same time. the 9th data bit is most commonly used as an ex tra stop bit or it can also be used as a parity bit (see ta bl e 6 - 1 ). 1 (set) ? start bit, 9 data bits, 1 stop bit. 0 (clear) ? start bit, 8 data bits, 1 stop bit. wake ? wake-up mode select this bit allows the user to se lect the method for receiver wa ke-up. the wake bit can be read or written to any time. see ta b l e 6 - 1 . 1 (set) ? wake-up on address mark; if rwu is set, sci will wake-up if the 8th (if m=0) or 9th (if m=1) bit received on the rx line is set. 0 (clear) ? wake-up on idle line; if rwu is set, sci will wake-up after 11 (if m=0) or 12 (if m=1) consecutive ?1?s on the rx line. table 6-1 method of receiver wake-up wake m method of receiver wake-up 0x detection of an idle line allows the next data type received to cause the receive data register to fill and produce an rdrf flag. 10 detection of a received one in t he eighth data bit allows an rdrf flag and associated error flags. 11 detection of a received one in the ninth data bit allows an rdrf flag and associated error flags. x = don?t care 71
freescale 6-12 mc68HC05B6 rev. 4.1 serial communications interface 6 cpol ? clock polarity this bit allows the user to select the polarity of the clocks to be sent to the sclk pin. it works in conjunction with the cpha bit to produce the desired clock-data relation (see figure 6-9 and figure 6-10 ). 1 (set) ? steady high value at sclk pin outside transmission window. 0 (clear) ? steady low value at sclk pin outside transmission window. this bit should not be manipulated while the transmitter is enabled. cpha ? clock phase this bit allows the user to select the phase of the clocks to be sent to the sclk pin. this bit works in conjunction with the cpol bit to produce the desired clock-data relation (see figure 6-9 and figure 6-10 ). 1 (set) ? sclk clock line activated at beginning of data bit. 0 (clear) ? sclk clock line activated in middle of data bit. this bit should not be manipulated while the transmitter is enabled. figure 6-9 sci data clock timing diagram (m=0) idle or preceding transmission clock stop start lsb data m = 0 (8 data bits) idle or next lbcl bit controls last data clock transmission clock clock clock * * * * * start stop 0123456 msb 7 (cpol = 0, cpha = 0) (cpol = 0, cpha = 1) (cpol = 1, cpha = 0) (cpol = 1, cpha = 1) 71
mc68HC05B6 rev. 4.1 freescale 6-13 serial communications interface 6 lbcl ? last bit clock this bit allows the user to select whether the cl ock associated with the last data bit transmitted (msb) has to be output to the sclk pin. the clock of the last data bit is output to the sclk pin if the lbcl bit is a logic one, and is not output if it is a logic zero. the last bit is the 8th or 9th da ta bit transmitted depending on the 8 or 9 bit format selected by m-bit (see ta bl e 6 - 2 ). this bit should not be manipulated while the transmitter is enabled. figure 6-10 sci data clock timing diagram (m=1) table 6-2 sci clock on sclk pin data format m-bit lbcl bit number of clocks on sclk pin 8 bit 0 0 7 8 bit 0 1 8 9 bit 1 0 8 9 bit 1 1 9 idle or preceding transmission clock stop start lsb data m = 1 (9 data bits) idle or next lbcl bit controls last data clock transmission clock clock clock * * * * start stop 0123456 msb 7 * 8 (cpol = 0, cpha = 0) (cpol = 0, cpha = 1) (cpol = 1, cpha = 0) (cpol = 1, cpha = 1) 71
freescale 6-14 mc68HC05B6 rev. 4.1 serial communications interface 6 6.11.3 serial communications control register 2 (sccr2) the sci control register 2 (sccr2) provides the co ntrol bits that enable/disable individual sci functions. tie ? transmit interrupt enable 1 (set) ? tdre interrupts enabled. 0 (clear) ? tdre interrupts disabled. tcie ? transmit complete interrupt enable 1 (set) ? tc interrupts enabled. 0 (clear) ? tc interrupts disabled. rie ? receiver interrupt enable 1 (set) ? rdrf and or interrupts enabled. 0 (clear) ? rdrf and or interrupts disabled. ilie ? idle line interrupt enable 1 (set) ? idle interrupts enabled. 0 (clear) ? idle interrupts disabled. te ? transmitter enable when the transmit enable bit is set, the transmit shift register output is applied to the tdo line and the corresponding clocks are applied to the sclk pin. depending on the st ate of control bit m (sccr1), a preamble of 10 (m = 0) or 11 (m = 1) consecutive ones is transmitted when software sets the te bit from a cleared state. if a transmission is in progress and a zero is writ ten to te, the transmitter will wait until after the present byte has been transmitted before placin g the tdo and the sclk pin in the idle, high impedance state. if the te bit has been written to a zero and then set to a one before the current byte is transmitted, the transmitter will wait for that byte to be trans mitted and will then initiate transmission of a new preamble. after this latest transmission, and provided the tdre bit is set (no new data to transmit), the line remains idle (driven high while te = 1); otherwise, normal transmission occurs. this function allows the user to neatly terminate a transmission sequence. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset sci control (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 71
mc68HC05B6 rev. 4.1 freescale 6-15 serial communications interface 6 after loading the last byte in the serial communica tions data register and receiving the tdre flag, the user should clear te. transmission of the last byte will then be completed and the line will go idle. 1 (set) ? transmitter enabled. 0 (clear) ? transmitter disabled. re ? receiver enable 1 (set) ? receiver enabled. 0 (clear) ? receiver disabled. when re is clear (receiver disabled) all the status bits associated with the receiver (rdrf, idle, or, nf and fe) are inhibited. rwu ? receiver wake-up when the receiver wake-up bit is set by the user software, it puts the receiver to sleep and enables the wake-up function. the type of wake-up mode for the receiver is determined by the wake bit discussed above (in the sccr1). when the rwu bit is set, no status flags will be set. flags which were set previously will not be cleared when rwu is set. if the wake bit is cleared, rwu is cleared by the sci logic after receiving 10 (m = 0) or 11 (m =1) consecutive ones. under these conditions, rwu cannot be set if the line is idle. if the wake bit is set, rwu is cleared after receiving an address bit. the rdrf flag will then be set and the address byte stored in the receiver data register. sbk ? send break if the send break bit is toggled set and cleared, the transmitter sends 10 (m = 0) or 11 (m = 1) zeros and then reverts to idle sending data. if sbk remains set, the transmitter will continually send whole blocks of zeros (sets of 10 or 11) unt il cleared. at the completion of the break code, the transmitter sends at least one high bit to guarantee recognition of a valid start bit. 71
freescale 6-16 mc68HC05B6 rev. 4.1 serial communications interface 6 6.11.4 serial communicati ons status register (scsr) the serial communications status re gister (scsr) provides inputs to the interrupt logic circuits for generation of the sci system interrupt. in addition, a noise flag bit and a framing error bit are also contained in the scsr. tdre ? transmit data register empty flag this bit is set when the contents of the transmit data register are transferred to the serial shift register. new data will not be transmitted unless the scsr register is read before writing to the transmit data register to clear the tdre flag. if the tdre bit is clear, this indicates that the transfer has not yet occurred and a write to the serial communications data register will overwrite the previous value. the tdre bit is cleared by accessing the serial communications status regist er (with tdre set) followed by writing to the serial communications data register. tc ? transmit complete flag this bit is set to indicate that the sci transmit ter has no meaningful information to transmit (no data in shifter, no preamble, no break). when tc is set the serial line will go idle (continuous mark). the tc bit is cleared by accessing the se rial communications status register (with tc set) followed by writing to the serial communications data register. it does not inhibit the transmitter function in any way. rdrf ? receive data register full flag this bit is set when the contents of the receiver se rial shift register are transferred to the receiver data register. if multiple errors are detected in any one receiv ed word, the nf and rdrf bits will be affected as appropriate during the same clock cycle. the rdrf bit is cleared when the serial communications status register is accessed (with rdrf set) foll owed by a read of the serial communications data register. idle ? idle line detected flag this bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven consecutive ?1?s). this bit will not be set by the idle line condition when the rwu bit is set. this allows a receiver that is not in the wake-up mode to detect the end of a message, detect the preamble of a new message or resynchronize with the transmitter. the idle bit is cleared by accessing the serial communications status register (with idle set) followed by a read of the serial communications data register. once cleared, id le will not be set again until after rdrf has been set, (i.e. until after the line has been active and becomes idle again). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u 71
mc68HC05B6 rev. 4.1 freescale 6-17 serial communications interface 6 or ? overrun error flag this bit is set when a new byte is ready to be tr ansferred from the receiver shift register to the receiver data register and the rece ive data register is already full (rdrf bit is set). data transfer is inhibited until the rdrf bit is cleared. data in the serial communications data register is valid in this case, but additional data received during an overrun condition (including the byte causing the overrun) will be lost. the or bit is cleared when the serial communications status register is accessed (with or set) followed by a read of the serial communications data register. nf ? noise error flag this bit is set if there is noise on a ?valid? start bi t, any of the data bits or on the stop bit. the nf bit is not set by noise on the idle line nor by invalid start bits. if there is noise, the nf bit is not set until the rdrf flag is set. each data bit is sampled three times as described in section 6.7 . the nf bit represents the status of the byte in the serial communications data register. for the byte being received (shifted in) there will be also a ?working? noise flag, the value of which will be transferred to the nf bit when the serial data is loaded into the serial communications data register. the nf bit does not generate an inte rrupt because the rdrf bi t gets set with nf and can be used to generate the interrupt. the nf bit is cleared when the serial communicat ions status register is accessed (with nf set) followed by a read of the serial communications data register. fe ? framing error flag this bit is set when the word boundaries in the bit stream are not synch ronized with the receiver bit counter (generated by the reception of a logi c zero bit where a stop bit was expected). the fe bit reflects the status of the byte in the receive data register and the transfe r from the receive shifter to the receive data register is inhibited by an overrun. the fe bit is set during the same cycle as the rdrf bit but does not get set in the case of an overrun (or). the framing error flag inhibits further transfer of data into the rece ive data register until it is cleared. the fe bit is cleared when the serial communica tions status register is accessed (with fe set) followed by a read of the serial communications data register. 71
freescale 6-18 mc68HC05B6 rev. 4.1 serial communications interface 6 6.11.5 baud rate register (baud) the baud rate register provides the means to select two different or equivalent baud rates for the transmitter and receiver. scp1, scp0 ? serial prescaler select bits these read/write bits determine the prescale fact or, np, by which the internal processor clock is divided before it is applied to the transmitter a nd receiver rate control dividers, nt and nr. this common prescaled output is used as the input to a divider that is controlled by the scr0?scr2 bits for the sci receiver, and by the sct0?sct2 bits for the transmitter. sct2, sct1,sct0 ? sci rate select bits (transmitter) these three read/write bits select the baud rates for the transmitter. the prescaler output is divided by the factors shown in ta b l e 6 - 4 . address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset sci baud rate (baud) $000d scp1 scp0 sct2 sct1 sct0 scr2 scr1 scr0 00uu uuuu table 6-3 first prescaler stage scp1 scp0 prescaler division ratio (np) 00 1 01 3 10 4 11 13 table 6-4 second prescaler stage (transmitter) sct2 sct1 sct0 transmitter division ratio (nt) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 71
mc68HC05B6 rev. 4.1 freescale 6-19 serial communications interface 6 scr2, scr1, scr0 ? sci rate select bits (receiver) these three read/write bits sele ct the baud rates for the receiv er. the prescaler output described above is divided by the factors shown in ta b l e 6 - 5 . the following equations are used to calculat e the receiver and transmitter baud rates: where: np = prescaler divide ratio nt = transmitter baud rate divide ratio nr = receiver baud rate divide ratio baudtx = transmitter baud rate baudrx = receiver baud rate f osc = oscillator frequency 6.12 baud rate selection the flexibility of the baud rate generator allo ws many different baud rates to be selected. a particular baud rate may be generated in several ways by manipulating the various prescaler and division ratio bits. ta b l e 6 - 6 shows the baud rates that can be achieved, for five typical crystal frequencies. these are effectively the highest baud rates which can be achieved using a given crystal. table 6-5 second prescaler stage (receiver) scr2 scr1 scr0 receiver division ratio (nr) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 128 baudtx f op 16 np nt ?? ---------------------------------- - = baudrx f op 16 np nr ?? ----------------------------------- = 71
freescale 6-20 mc68HC05B6 rev. 4.1 serial communications interface 6 note: the examples shown above do not apply when the part is operating in slow mode (see section 2.4.3 ). table 6-6 sci baud rate selection crystal frequency ? f osc (mhz) scp1 scp0 sct/r2 sct/r1 sct/r0 np nt/nr 4.194304 4.00 2.4576 2.00 1.8432 0 0 0 0 0 1 1 131072 125000 76800 62500 57600 0 0 0 0 1 1 2 65536 62500 38400 31250 28800 0 0 0 1 0 1 4 32768 31250 19200 15625 14400 0 0 0 1 1 1 8 16384 15625 9600 7813 7200 0 0 1 0 0 1 16 8192 7813 4800 3906 3600 0 0 1 0 1 1 32 4096 3906 2400 1953 1800 0 0 1 1 0 1 64 2048 1953 1200 977 900 0 0 1 1 1 1 128 1024 977 600 488 450 0 1 0 0 0 3 1 43691 41667 25600 20833 19200 0 1 0 0 1 3 2 21845 20833 12800 10417 9600 0 1 0 1 0 3 4 10923 10417 6400 5208 4800 0 1 0 1 1 3 8 5461 5208 3200 2604 2400 0 1 1 0 0 3 16 2731 2604 1600 1302 1200 0 1 1 0 1 3 32 1365 1302 800 651 600 0 1 1 1 0 3 64 683 651 400 326 300 0 1 1 1 1 3 128 341 326 200 163 150 1 0 0 0 0 4 1 32768 31250 19200 15625 14400 1 0 0 0 1 4 2 16384 15625 9600 7813 7200 1 0 0 1 0 4 4 8192 7813 4800 3906 3600 1 0 0 1 1 4 8 4096 3906 2400 1953 1800 1 0 1 0 0 4 16 2048 1953 1200 977 900 1 0 1 0 1 4 32 1024 977 600 488 450 1 0 1 1 0 4 64 512 488 300 244 225 1 0 1 1 1 4 128 256 244 150 122 113 1 1 0 0 0 13 1 10082 9615 5908 4808 4431 1 1 0 0 1 13 2 5041 4808 2954 2404 2215 1 1 0 1 0 13 4 2521 2404 1477 1202 1108 1 1 0 1 1 13 8 1260 1202 738 601 554 1 1 1 0 0 13 16 630 601 369 300 277 1 1 1 0 1 13 32 315 300 185 150 138 1 1 1 1 0 13 64 158 150 92 75 69 111111312879 75 46 38 35 71
mc68HC05B6 rev. 4.1 freescale 6-21 serial communications interface 6 6.13 sci during stop mode when the mcu enters stop mode, the baud rate gen erator driving the receiver and transmitter is shut down. this stops all sci activity. both the receiver and the transmitter are unable to operate. if the stop instruction is executed during a tr ansmitter transfer, that transfer is halted. when stop mode is exited as a result of an external interrupt, that particular transmission resumes. if the receiver is receiving data when the stop instruction is executed, received data sampling is stopped (baud generator stops) and the rest of the data is lost. warning: for the above reasons, all sci transactions should be in the idle state when the stop instruction is executed. 6.14 sci during wait mode the sci system is not af fected by wait mode a nd continues normal oper ation. any valid sci interrupt will wake-up the system. if required, th e sci system can be disabled prior to entering wait mode by writing a zero to the transmitter and receiver enable bits in the serial communication control register 2 at $000f. this action will result in a reduction of power consumption during wait mode. 71
freescale 6-22 mc68HC05B6 rev. 4.1 serial communications interface 6 this page left bl ank intentionally 71
mc68HC05B6 rev. 4.1 freescale 7-1 pulse length d/a converters 7 7 pulse length d/a converters the pulse length d/a converter (plm) system works in conjunction with the timer to execute two 8-bit d/a conversions, with a choice of two repetition rates. (see figure 7-1 .) figure 7-1 plm system block diagram plma register plmb ?a? register buffer ?b? register ?a? comparator ?b? latch zero detector sfa bit sfb d/a pin timer bus from timer d a t a b us 8 16 multiplexer ?a? ?b? buffer register comparator multiplexer plma plmb d/a r s bit zero detector 8 16 88 pin latch r s
freescale 7-2 mc68HC05B6 rev. 4.1 pulse length d/a converters 7 the d/a converter has two data register s associated with it, plma and plmb. this is a dual 8-bit resolution d/a converter a ssociated with two output pins (plma and plmb). the outputs are pulse length m odulated signals whos e duty cycle ratio may be modified. these signals can be used directly as plms, or the f iltered average may be used as general purpose analog outputs. the longest repetition period is 4096 times the programmable timer clock period (cpu clock multiplied by four), and the shortest repetition period is 256 times the programmable timer clock period (the repetition rate frequencies for a 4 mhz crystal are 122 hz and 1953 hz respectively). registers plma ($0a) and plmb ($0b) are associat ed with the pulse length values of the two counters. a value of $00 loaded into these regist ers results in a continuously low output on the corresponding d/a output pin. a value of $80 results in a 50% duty cycle output , and so on, to the maximum value $ff corresponding to an output whic h is at ?1? for 255/256 of the cycle. when the mcu makes a write to register plma or plmb the new value will only be picked up by the d/a converters at the end of a complete cycle of conversion. this results in a monotonic change of the dc component at the output without overshoots or vicious starts (a vicious start is an output which gives totally erroneous plm during the period immediately following an update of the plm d/a registers). this feature is achieved by double buffering of the plm d/a registers. examples of pwm output waveforms are shown in figure 7-2 . address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 figure 7-2 plm output waveform examples 256 t 255 t 128 t t $80 $ff t = 4 cpu clocks in fast mode and 64 cpu clocks in slow mode 128 t t $00 $01 255 t
mc68HC05B6 rev. 4.1 freescale 7-3 pulse length d/a converters 7 note: since the plm system uses the timer counter, plm results will be affected while resetting the timer counter. both d/a registers are reset to $00 during power-on or external reset. wait mode does not affect the output waveform of the d/a converters. 7.1 miscellaneous register sfa ? slow or fast mode selection for plma this bit allows the user to select the slow or fast mode of the plma pulse length modulation output. 1 (set) ? slow mode plma (4096 x timer clock period). 0 (clear) ? fast mode plma (256 x timer clock period). sfb ? slow or fast mode selection for plmb this bit allows the user to select the slow or fast mode of the plmb pulse length modulation output. 1 (set) ? slow mode plmb (4096 x timer clock period). 0 (clear) ? fast mode plmb (256 x timer clock period). the highest speed of the plm system corresponds to the frequency of the tof bit being set, multiplied by 256. the lowest speed of the pl m system corresponds to the frequency of the tof bit being set, multiplied by 16. because the sf a bit and sfb bit are not double buffered, it is mandatory to set them to the desired values before writing to the plm registers; not doing so could temporarily give incorrect values at the plm outputs. sm ? slow mode 1 (set) ? the system runs at a bus speed 16 times lower than normal (f osc /32). slow mode affects all sections of the device, including sci, a/d and timer. 0 (clear) ? the system runs at normal bus speed (f osc /2). address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous $000c por intp intn inte sfa sfb sm wdog ?001 000?
freescale 7-4 mc68HC05B6 rev. 4.1 pulse length d/a converters 7 the sm bit is cleared by external or power-on reset. the sm bit is aut omatically cleared when entering stop mode. note: the bits that are shown shaded in the ab ove representation are explained individually in the relevant sections of this manual. the complete register plus an explanation of each bit can be found in section 3.8 7.2 plm clock selection the slow/fast mode of the plm d/a converters is selected by bits 1, 2, and 3 of the miscellaneous register at address $000c (sfa bit for plma a nd sfb bit for plmb). the slow/fast mode has no effect on the d/a converters? 8-bit resolution (see figure 7-3 ). 7.3 plm during stop mode on entering stop mode, the plm outputs remain at their particular level. when stop mode is exited by an interrupt, the plm sy stems resume regular operation. if stop mode is exited by power-on or external reset the registers values are forced to $00. 7.4 plm during wait mode the plm system is not affected by wait mode and continues normal operation. figure 7-3 plm clock selection f osc 2 32 sm bit = 0 sm bit = 1 4 x4096 x256 sf bit = 1 sf bit = 0 timer clock plm clock bus frequency (f op )
mc68HC05B6 rev. 4.1 freescale 8-1 analog to digital converter 8 8 analog to digital converter the analog to digital converte r system consists of a single 8-bit successive approximation converter and a sixteen channel multiplexer. eight of the channels are connected to the pd0/an0 ? pd7/an7 pins of the mc68HC05B6 an d the other eight cha nnels are dedicated to internal reference points for test functions. the channel input pins do not have any internal output driver circuitry connected to them because such circuitry would load the analog input signals due to output buffer leakage current. there is one 8- bit result data register (address $08) and one 8-bit status/control regi ster (address $09). the a/d converter is ratiometric and two dedicate d pins, vrh and vrl, are used to supply the reference voltage levels for all analog inputs. these pins are us ed in preference to the system power supply lines because any voltage drops in the bonding wires of the heavily loaded supply pins could degrade the accuracy of the a/d conversion. an input voltage equal to or greater than v rh converts to $ff (full scale) with no overflow indication and an input voltage equal to v rl converts to $00. the a/d converter can operate from either the bus clock or an internal rc type oscillator. the internal rc type oscillator is activated by the a drc bit in the a/d status/c ontrol register (adstat) and can be used to give a sufficiently high clock rate to the a/d converter when the bus speed is too low to provide accurate results. when the a/d co nverter is not being used it can be disconnected, by clearing the adon bit in the adstat register, in order to save power (see section 8.2.3 ). for further information on a/d converter operation please refer to the m68hc11 reference manual ? m68hc11rm/ad. 8.1 a/d converter operation the a/d converter consists of an analog multiplexe r, an 8-bit digital to analog converter capacitor array, a comparator and a successive approximation register (sar) (see figure 8-1 ). there are eleven options that can be selected by the multiplexer; an 0?an7, vrh, (vrh+vrl)/2 or vrl. selection is done via the chx bits in the adstat register (see section 8.2.3 ). an0?an7 are the only input points for a/d conversion operat ions; the others are reference points that can be used for test purposes.
freescale 8-2 mc68HC05B6 rev. 4.1 analog to digital converter 8 the a/d reference input (an0?an7) is applied to a precision internal d/a converter. control logic drives this d/a converter and the analog output is successively compared with the analog input sampled at the beginning of the conversion. the conversion is monotonic with no missing codes. the result of each successive comparison is st ored in the sar and, when the conversion is complete, the contents of the sar are transferred to the read-only result data register ($08), and the conversion complete flag, coco, is set in the a/d status/control register ($09). warning: any write to the a/d status/con trol register will abort the current conversion, reset the conversion complete flag and start a new conversion on the selected channel. at power-on or external reset, both the adrc and adon bits are cleared; thus the a/d is disabled. figure 8-1 a/d converter block diagram an0 vrh (vrh+vrl)/2 vrl analog mux a/d result register (addata) $08 8-bit capacitive dac with sample and hold vrh vrl result a/d status/control register (adstat)$09 (channel assignment) coco adrc adon 0 ch3 ch2 ch1 ch0 an1 an2 an3 an4 an5 an6 an7 successive approximation register (sar) and control
mc68HC05B6 rev. 4.1 freescale 8-3 analog to digital converter 8 8.2 a/d registers 8.2.1 port d data register (portd) port d is an input-only port which routes the ei ght analog inputs to the a/d converter. when the a/d converter is disabled, the pins are configured as standard input-only port pins, which can be read via the port d data register. note: when the a/d function is enabled, pins pd0? pd7 will act as analog inputs. using a pin or pins as a/d inputs does not affect the ability to read port d as static inputs; however, reading port d during an a/d conversion sequence may inject noise on the analog inputs and result in reduced accuracy of the a/d result. performing a digital read of port d with levels other than v dd or v ss on the pins will result in greater power dissi pation during the read cycle, and ma y give unpredictable results on the corresponding port d pins. 8.2.2 a/d result data register ( addata ) addata is a read-only register which is used to store the results of a/d conversions. each result is loaded into the register from the sar and t he conversion complete flag, coco, in the adstat register is set. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 undefined address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset a/d data (addata) $0008 0000 0000
freescale 8-4 mc68HC05B6 rev. 4.1 analog to digital converter 8 8.2.3 a/d status/control register (adstat) coco ? conversion complete flag 1 (set) ? coco is set each time a conversion is complete, allowing the new result to be read from the a/d result data register ($08). the converter then starts a new conversion. 0 (clear) ? coco is cleared by reading the result data register or writing to the status/control register. reset clears the coco flag. adrc ? a/d rc oscillator control the adrc bit allows the user to control the a/d rc oscillator, which is used to provide a sufficiently high clock rate to the a/d to ensure accuracy when the chip is running at low speeds. 1 (set) ? when the adrc bit is set, the a/ d rc oscillator is turned on and, if adon is set, the a/d runs from the rc oscillator clock. see ta bl e 8 - 1 . 0 (clear) ? when the adrc bit is cleared, the a/d rc oscillator is turned-off and, if adon is set, the a/d runs from the cpu clock. when the a/d rc oscillator is turned on, it takes a time t adrc to stabilize (see table 11-6 and table 11-7 ). during this time a/d conversion results may be inaccurate. note: if the mcu bus clock falls below 1mhz, the a/d rc oscillator should be switched on. power-on or external reset clears the adrc bit. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 table 8-1 a/d clock selection adrc adon rc oscillator a/d converter comments 0 0 off off a/d switched off. 0 1 off on a/d using cpu clock. 1 0 on off allows the rc oscillator to stabilize. 1 1 on on a/d using rc oscillator clock.
mc68HC05B6 rev. 4.1 freescale 8-5 analog to digital converter 8 adon ? a/d converter on the adon bit allows the user to enable/disable the a/d converter. 1 (set) ? a/d converter is switched on. 0 (clear) ? a/d converter is switched off. when the a/d converter is switched on, it takes a time t adon for the current sources to stabilize (see table 11-6 and table 11-7 ). using the a/d converter before this time has elapsed may result in the incorrect operation of the a/d, even after t adon has elapsed. in this case adon would have to be cleared and set again. power-on or external reset will clear the adon bit, thus disabling the a/d converter. ch3?ch0 ? a/d channels 3, 2, 1 and 0 the ch3?ch0 bits allow the user to determine which channel of the a/d converter multiplexer is selected. see ta bl e 8 - 2 for channel selection. reset clears the ch0?ch3 bits. table 8-2 a/d channel assignment ch3 ch2 ch1 ch0 channel selected 0000 an0 0001 an1 0010 an2 0011 an3 0100 an4 0101 an5 0110 an6 0111 an7 1 0 0 0 vrh pin (high) 1001 (vrh + vrl) / 2 1 0 1 0 vrl pin (low) 1 0 1 1 vrl pin (low) 1 1 0 0 vrl pin (low) 1 1 0 1 vrl pin (low) 1 1 1 0 vrl pin (low) 1 1 1 1 vrl pin (low)
freescale 8-6 mc68HC05B6 rev. 4.1 analog to digital converter 8 8.3 a/d converter during stop mode when the mcu enters stop mode with the a/d converter turned on, the a/d clocks are stopped and the a/d converter is disabled for the duration of stop mode, including the 4064 cycles start-up time. if the a/d rc oscillator is in operation it will also be disabled. 8.4 a/d converter during wait mode the a/d converter is not affected by wa it mode and continues normal operation. in order to reduce power consumption the a/d converter can be disconnected, under software control using the adon bit and the adrc bit in the a/d status/control register at $0009, before entering wait mode. 8.5 port d analog input the external analog voltage value to be processed by the a/d converter is sampled on an internal capacitor through a resistive path, provided by i nput-selection switches and a sampling aperture time switch, as shown in figure 8-2 . sampling time is limited to 12 bus clock cycles. after sampling, the analog value is stored on the capacit or and held until the end of conversion. during this hold time, the analog input is disconnected from the inte rnal a/d system and the external voltage source sees a high impedance input. the equivalent analog input during sampling is an rc low-pass filter with a minimum resistance of 50 k ? and a capacitance of at least 10pf. it should be noted that these are typical values measured at room temperature. figure 8-2 electrical model of an a/d input pin analog input pin input protection device v rl < 2pf + 20v - 0.7v 1 a junction leakage 50k ? 10pf dac capacitance note: the analog switch is closed during the 12 cycle sample time only.
mc68HC05B6 rev. 4.1 freescale 9-1 resets and interrupts 9 9 resets and interrupts 9.1 resets the mc68HC05B6 can be reset in three ways: by the initial power-on reset function, by an active low input to the reset pin or by a computer operating properly (cop) watchdog reset. any of these resets will cause the program to go to it s starting address, spec ified by the contents of memory locations $1ffe and $1fff, and cause the interrupt mask bit in the condition code register to be set. figure 9-1 reset timing diagram v dd reset 1fff 1ffe 1ffe 1ffe new 1fff 1ffe 1ffe 1ffe pc osc1 new pc internal internal processor clock 1ffe op code new pcl new pch t vddr op code new pcl new pch address bus internal data bus t oxov t cyc t porl 1ffe program execution begins program execution begins t rl (or t dogl ) (internal power-on reset) (external hardware reset) v dd threshold (1-2v typical) reset sequence reset sequence
freescale 9-2 mc68HC05B6 rev. 4.1 resets and interrupts 9 9.1.1 power-on reset a power-on reset occurs when a positive transition is detected on vdd. the power-on reset function is strictly for power turn-on conditions and should not be used to detect drops in the power supply voltage. the power-on circuitry provides a stabilization delay (t porl ) from when the oscillator becomes active. if the external reset pin is low at the end of this delay then the processor remains in t he reset state until reset goes high. the user must ensure that the voltage on vdd has risen to a point where the mcu can operate properly by the time t porl has elapsed. if there is doubt, the ex ternal reset pin should remain low until the voltage on vdd has reached the specified minimum operating voltage. this may be accomplished by connecting an external rc circuit to this pin to generate a power-on reset (por). in this case, the time constant must be great enough to allow the oscillator circuit to stabilize. during power-on reset, the reset pin is driven low during a t porl delay start-up sequence. t porl is defined by a user specified mask option to be either 16 cycles or 4064 cycles (see section 1.2 ). a software distinction between a power-on reset and an external reset can be made using the por bit in the miscellaneous register (see section 9.1.2 ). 9.1.2 miscellaneous register por ? power-on reset bit this bit is set each time the device is powered on. therefore, the state of the por bit allows the user to make a software distinction between a po wer-on and an external reset. this bit cannot be set by software and is cleared by writing it to zero. 1 (set) ? a power-on reset has occurred. 0 (clear) ? no power-on reset has occurred. note: the bits shown shaded in the above repres entation are explained individually in the relevant sections of this manual. the comple te register plus an explanation of each bit can be found in section 3.8 . address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous $000c por (1) (1) the por bit is set each time there is a power-on reset. intp intn inte sfa sfb sm wdog (2) (2) the state of the wdog bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled. ?001 000?
mc68HC05B6 rev. 4.1 freescale 9-3 resets and interrupts 9 9.1.3 reset pin when the oscillator is running in a stable condition, the mcu is reset when a logic zero is applied to the reset input for a minimum period of 1.5 machine cycles (t cyc ). an internal schmitt trigger is used to improve noise immunity on this pin. when the reset pin goes high, the mcu will resume operation on the fo llowing cycle. when a reset condition occurs internally, i.e. from por or the cop watchdog, the reset pin provides an active-low open drain output signal which may be used to reset external hardware. current limitation to protect the pull-down device is provided in case an rc type external reset circuit is used. 9.1.4 computer operating pr operly (cop) watchdog reset the watchdog counter system cons ists of a divide-by-8 counter, preceded by a fixed divide-by-4 and a fixed divide-by-256 prescaler, plus control logic as shown in figure 9-2 . the divide-by-8 counter can be reset by software. warning: the input to the watchdog system is derived from the carry output of bit 7 of the free running timer counter. therefore, a reset of the timer may affect the period of the watchdog timeout. the watchdog system can be automatic ally enabled, following power-on or external reset, via a mask option (see section 1.2 ), or it can be enabled by software by writing a ?1? to the wdog bit in the miscellaneous register at $000c (see section 9.1.2 ). once enabled, the watchdog system figure 9-2 watchdog system block diagram 256 (bit 7 of free f osc /2 f osc /32 main cpu 8 watchdog counter wdog bit control logic latch + reset schmitt input protection trigger pin power-on s r enable reset clock 4 prescaler running counter)
freescale 9-4 mc68HC05B6 rev. 4.1 resets and interrupts 9 cannot be disabled by software (writing a ?zero? to the wdog bit has no effect at any time). in addition, the wdog bit acts as a reset mechanism for the watchdog counter. writing a ?1? to this bit clears the counter to its initial value and prevents a watchdog timeout. wdog ? watchdog enable/disable the wdog bit can be used to enable the watchdog timer previously disabled by a mask option. following a watchdog reset the state of the wdog bit is as defined by the mask option specified. 1 (set) ? watchdog enabled and counter cleared. 0 (clear) ? the watchdog cannot be disabled by software; writing a zero to this bit has no effect. the divide-by-8 watchdog counter will generate a main reset of the chip when it reaches its final state; seven clocks are necessary to bring the watchdog counter from its clear state to its final state. this reset appears after time t dog since the last clear or since the enable of the watchdog counter system. the watchdog counter, therefore, has to be cleared periodically, by software, with a period less than t dog . the reset generated by the watchd og system is apparent at the reset pin (see figure 9-2 ). the reset pin level is re-entered in the control logic, and when it has been maintained at level ?zero? for a minimum of t dogl , the reset pin is released. 9.1.4.1 cop watchdog during stop mode the stop instruction is inhibited when the watch dog system is enabled. if a stop instruction is executed while the watchdo g system is enabled, th en a watchdog reset will occur as if there were a watchdog timeout. in the case of a watchdog rese t due to a stop instruction, the oscillator will not be affected, thus there will be no t porl cycles start-up delay. on start-up, the watchdog will be configured according to the user specified mask option. 9.1.4.2 cop watchdog during wait mode the state of the watchdog during wait mode is selected via a mask option (see section 1.2 ) to be one of the options below: watchdog enabled ? the watchdog counter will continue to operate during wait mode and a reset will occur after time t dog . watchdog disabled ? on enterin g wait mode, the watchdog counter system is reset and disabled. on exiting wait mode the counter resumes normal operation.
mc68HC05B6 rev. 4.1 freescale 9-5 resets and interrupts 9 9.1.5 functions affected by reset when processing stops within the mcu for any reason, i.e. power-on reset, external reset or the execution of a stop or wait instruction, vari ous internal functions of the mcu are affected. ta b l e 9 - 1 shows the resulting action of any type of sy stem reset, but not necessarily in the order in which they occur. table 9-1 effect of reset , por, stop and wait function/effect reset por wait stop timer prescaler set to zero x x ? ? timer counter set to $fffc x x ? ? all timer enable bits cleared (disable) x x ? ? data direction registers cleared (inputs) x x ? ? stack pointer set to $00ff x x ? ? force internal address bus to restart x x ? ? vector $1ffe, $1fff x x ? ? interrupt mask bit (i-bit ccr) set to 1 x x ? ? interrupt mask bit (i -bit ccr) cleared ? ? x x set interrupt enable bit (inte) x x ? ? set por bit in miscellaneous register ? x ? ? reset stop latch x x ? ? reset irq latch x x ? ? reset wait latch x x ? ? sci disabled x x ? ? sci status bits cleared (except tdre and tc) x x ? ? sci interrupt enable bits cleared x x ? ? sci status bits tdre and tc set x x ? ? oscillator disabled for 4064 cycles ? x ? x timer clock cleared ? x ? x sci clock cleared ? x ? x a/d disabled x x ? x sm bit in the miscella neous register cleared x x ? x watchdog counter reset x x x x wdog bit in the miscellan eous register reset x x ? x eeprom control bits (see section 3.5.1 )xx?x x = described action takes place ? = described action does not take place
freescale 9-6 mc68HC05B6 rev. 4.1 resets and interrupts 9 9.2 interrupts the mcu can be interrupted by four different sources: three maskable hardware interrupts and one non maskable software interrupt: external signal on the irq pin serial communications interface (sci) programmable timer software interrupt instruction (swi) interrupts cause the processor to save the regist er contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. the rt i instruction (return from interrupt) causes the register contents to be recove red from the stack and normal processing to resume. while executing the rti instruction, the value of the i- bit is replaced by the corresponding i-bit stored on the stack. unlike reset, hardware interrupts do not cause th e current instruction execution to be halted, but are considered pending until the current instruction is complete. the current instruction is the one already fetched and being operated on. when the current instruction is complete, the processor checks all pending hardware interrupts. if interrupts are not masked (i-bit clear) and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. note: power-on and external reset clear all interrupt enable bits, but set the inte bit in the miscellaneous register, thus preventing interrupts during the reset sequence. 9.2.1 interrupt priorities each potential interrupt source is assigned a prio rity level, which means that if more than one interrupt is pending at the same time, the processor will service the one with the highest priority first. for example, if both an external interrupt an d a timer interrupt are pending after an instruction execution, the external interrupt is serviced first. ta b l e 9 - 2 shows the relative priority of all the possible interrupt sources. figure 9-3 shows the interrupt processing flow. 9.2.2 nonmaskable software interrupt (swi) the software interrupt (swi) is an executable instruction and a nonmaskable interrupt: it is executed regardless of the state of the i-bit in the ccr. if the i-bit is zero (interrupts enabled), swi is executed after interrupts that were pendi ng when the swi was fetched, but before interrupts
mc68HC05B6 rev. 4.1 freescale 9-7 resets and interrupts 9 generated after the swi was fetched. the swi inte rrupt service routine address is specified by the contents of memory locations $1ffc and $1ffd. 9.2.3 maskable hardware interrupts if the interrupt mask bit in the ccr is set, all maskable interrupts (internal and external) are masked. clearing the i-bit allows interrupt processing to occur. note: the internal interrupt latch is cleared in th e first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the i-bit is cleared. 9.2.3.1 external interrupt (irq ) if the interrupt mask in the condition code regi ster has been cleared and the interrupt enable bit (inte) is set and the signal on the external interrupt pin (irq ) satisfies the cond ition selected by the option control bits (intp and in tn), then the external interrupt is recognized. inte, intp and intn are all bits contained in the miscellane ous register at $000c. when the interrupt is recognized, the current state of the cpu is pus hed onto the stack and the i-bit is set. this masks further interrupts until the present one is servic ed. the external interrupt service routine address is specified by the content of memory locations $1ffa and $1ffb. table 9-2 interrupt priorities source register flags vector address priority reset ? ? $1ffe, $1fff highest software interrupt (swi) ? ? $1ffc, $1ffd external interrupt (irq ) ? ? $1ffa, $1ffb timer input captures tsr icf1, icf2 $1ff8, $1ff9 timer output compares tsr ocf1, ocf2 $1ff6, $1ff7 timer overflow tsr tof $1ff4, $1ff5 serial communications interface (sci) scsr tdre, tc, or, rdrf, idle $1ff2, $1ff3 lowest
freescale 9-8 mc68HC05B6 rev. 4.1 resets and interrupts 9 figure 9-3 interrupt flow chart reset is i-bit set? irq external interrupt? timer internal interrupt? sci internal interrupt? fetch next instruction execute instruction clear irq request latch stack pc, x, a, cc set i-bit load pc from: irq: $1ffa-$1ffb timer ic: $1ff8-$1ff9 timer oc: $1ff6-$1ff7 timer ovf:$1ff4-$1ff5 sci: $1ff2-$1ff3 complete interrupt routine and execute rti
mc68HC05B6 rev. 4.1 freescale 9-9 resets and interrupts 9 9.2.3.2 miscella neous register note: the bits shown shaded in the above representation are explained individually in the relevant sections of this manual. the comple te register plus an explanation of each bit can be found in section 3.8 . intp, intn ? external inte rrupt sensitivity options these two bits allow the user to select which edge the irq pin is sensitive to as shown in ta bl e 9 - 3 . both bits can be written to only while the i-bit is set, and are cleared by power-on or external reset. therefore the device is initiali sed with negative edge and low level sensitivity. inte ? external interrupt enable 1 (set) ? external interrupt function (irq ) enabled. 0 (clear) ? external interrupt function (irq ) disabled. the inte bit can be written to only while the i-bit is set, and is set by power-on or external reset, thus enabling the external interrupt function. ta bl e 9 - 3 describes the various triggering options available for the irq pin, however it is important to re-emphasize here that in order to avoid any conflict and spurious interrupt, it is only possible to change the external interrupt options while the i-bit is set. any attempt to change the external interrupt option while the i-bit is clear will be unsucce ssful. if an external interrupt is pending, it will automatically be cleared when selecting a different interrupt option. note: if the external interrupt function is disabled by the inte bit and an external interrupt is sensed by the edge detector circuitry, then the interrupt request is latched and the interrupt stays pending until the inte bit is set. the internal latch of the external interrupt is cleared in the first part of the service routine (except for the low level address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset miscellaneous $000c por intp intn inte sfa sfb sm wdog ?001 000? table 9-3 irq sensitivity intp intn irq sensitivity 0 0 negative edge and low level sensitive 0 1 negative edge only 1 0 positive edge only 1 1 positive and negative edge sensitive
freescale 9-10 mc68HC05B6 rev. 4.1 resets and interrupts 9 interrupt which is not latched); therefore, only one external interrupt pulse can be latched during t ilil and serviced as soon as the i-bit is cleared. 9.2.3.3 timer interrupts there are five different timer interrupt flags (icf1, icf2, ocf1, ocf2 and tof) that will cause a timer interrupt whenever they are set and enabled. these five interrupt flags are found in the five most significant bits of the time r status register (tsr) at locati on $0013. icf1 and icf2 will vector to the service routine defined by $1ff8-$1ff9, oc f1 and ocf2 will vector to the service routine defined by $1ff6?$1ff7 and tof will vector to the service routine defined by $1ff4?$1ff5 as shown in figure 5.1 . there are three corresponding enable bits; icie for icf1 and icf2, ocie for ocf1 and ocf2, and toie for tof. these enable bits are located in the timer control regi ster (tcr) at address $0012. see section 5.2.1 and section 5.2.2 for further information. 9.2.3.4 serial communications interface (sci) interrupts there are five different interrupt flags (tdre, tc, or, rdrf and idle) that cause sci interrupts whenever they are set and enabled. these five inte rrupt flags are found in the five most significant bits of the sci status regist er (scsr) at location $0010. there are four corresponding enable bits: tie for tdre, tcie for tc, rie for or and rdrf, and ilie for idle. these enable bits are located in the serial communicat ions control register 2 (sccr2) at address $000f. see section 6.11.3 and section 6.11.4 . the sci interrupt causes the program counter to vector to the address pointed to by memory locations $1ff2 and $1ff3 which contain the star ting address of the interrupt service routine. software in the sci interrupt service routine must determine the priority and cause of the interrupt by examining the interrupt flags and the status bits located in the seri al communications status register scsr (address $0010). the general sequence for clearing an interrupt is a software sequence of accessing the serial communications status register while the flag is set followed by a read or write of an associated register. refer to section 6 for a description of the sci system and its interrupts.
mc68HC05B6 rev. 4.1 freescale 9-11 resets and interrupts 9 9.2.4 hardware controlled interrupt sequence the following three functions: reset, stop and wait, are not in the strictest sense interrupts. however, they are acted upon in a similar manner. flowcharts for stop and wait are shown in figure 2.4 . reset: a reset condition causes the program to vector to its starting address, which is contained in memory locations $1ffe (m sb) and $1fff (lsb). the i-bit in the condition code register is also set, to disable interrupts. stop: the stop instruction causes the oscillato r to be turned off and the processor to ?sleep? until an external interrupt (irq ) or occurs or the device is reset. wait: the wait instruction causes all processor clocks to stop, but leaves the timer clocks running. this ?rest? state of the processor ca n be cleared by reset, an external interrupt (irq ), a timer interrupt or an sci interrupt. th ere are no special wait vectors for these individual interrupts.
freescale 9-12 mc68HC05B6 rev. 4.1 resets and interrupts 9 this page left bl ank intentionally
mc68HC05B6 rev. 4.1 freescale 10-1 cpu core and instruction set 10 10 cpu core and instruction set this section provides a description of the cp u core registers, the instruction set and the addressing modes of the mc68HC05B6. 10.1 registers the mcu contains five registers, as shown in the programming model of figure 10-1 . the interrupt stacking order is shown in figure 10-2 . figure 10-1 programming model figure 10-2 stacking order accumulator index register program counter stack pointer condition code register carry / borrow zero negative interrupt mask half carry 70 70 15 7 0 0 15 7 0 0 0 0 0 0 0 0 1 1 70 1 1 1 h i n z c condition code register accumulator index register program counter high program counter low 70 stack unstack decreasing memory address increasing memory address interrupt return 115
freescale 10-2 mc68HC05B6 rev. 4.1 cpu core and instruction set 10 10.1.1 accumulator (a) the accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 10.1.2 index register (x) the index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. the index register may also be used as a temporary storage area. 10.1.3 program counter (pc) the program counter is a 16-bit register, which contai ns the address of the next byte to be fetched. 10.1.4 stack pointer (sp) the stack pointer is a 16-bit register, which c ontains the address of the next free location on the stack. during an mcu reset or the reset stack point er (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer is then decrem ented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the ten most significant bits are permanently set to 0000000011. these ten bits are appended to the six least significant register bits to produ ce an address within the range of $00c0 to $00ff. subroutines and interrupt s may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wrap s around and overwrites the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses five locations. 10.1.5 condition code register (ccr) the ccr is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. these bits can be individually tested by a program, and specific actions can be taken as a result of their state. each bit is explained in the following paragraphs. 115
mc68HC05B6 rev. 4.1 freescale 10-3 cpu core and instruction set 10 half carry (h) this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. interrupt (i) when this bit is set all maskable interrupts are masked. if an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. zero (z) when set, this bit indicates that the result of the la st arithmetic, logical, or data manipulation was zero. carry/borrow (c) when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is also affected during bit test and branch instructions and during shifts and rotates. 10.2 instruction set the mcu has a set of 62 basic instructions. th ey can be grouped into five different types as follows: ? register/memory ? read/modify/write ?branch ? bit manipulation ? control the following paragraphs briefly explain each ty pe. all the instructions within a given type are presented in individual tables. this mcu uses all the instructions available in the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. this instruct ion allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is then stored in the index register and the low-order product is stored in the accumulator. a detailed definition of the mul instruction is shown in ta bl e 1 0 - 1 . 115
freescale 10-4 mc68HC05B6 rev. 4.1 cpu core and instruction set 10 10.2.1 register/memory instructions most of these instructions use two operands. the first operand is either the accumulator or the index register. the second operand is obtained from memory using one of the addressing modes. the jump unconditional (jmp) and jump to su broutine (jsr) instructions have no register operand. refer to ta bl e 1 0 - 2 for a complete list of register/memory instructions. 10.2.2 branch instructions these instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. branch instructio ns are two-byte instructions. refer to table 10-3 . 10.2.3 bit manipulation instructions the mcu can set or clear any writable bit that re sides in the first 256 bytes of the memory space (page 0). all port data and data direction regist ers, timer and serial interface registers, control/status registers and a po rtion of the on-chip ram reside in page 0. an additional feature allows the software to test and branch on the stat e of any bit within these locations. the bit set, bit clear, bit test and branch functions are all impl emented with single instructions. for the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. refer to ta b l e 1 0 - 4 . 10.2.4 read/modify/wri te instructions these instructions read a memory location or a r egister, modify or test it s contents, and write the modified value back to memory or to the register. the test for negative or zero (tst) instruction is an exception to this sequence of reading, modifyin g and writing, since it does not modify the value. refer to ta b l e 1 0 - 5 for a complete list of read/modify/write instructions. 10.2.5 control instructions these instructions are register reference instru ctions and are used to control processor operation during program execution. refer to table 10-6 for a complete list of control instructions. 10.2.6 tables tables for all the instruction types listed above follow. in addition there is a complete alphabetical listing of all the instructions (see table 10-7 and ta b l e 1 0 - 8 ), and an opcode map for the instruction set of the m68hc05 mcu family (see ta bl e 1 0 - 9 ). 115
mc68HC05B6 rev. 4.1 freescale 10-5 cpu core and instruction set 10 table 10-1 mul instruction operation x:a x*a description multiplies the eight bits in the index register by the eight bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register. condition codes h : cleared i : not affected n : not affected z : not affected c : cleared source mul form addressing mode cycles bytes opcode inherent 11 1 $42 table 10-2 register/memory instructions addressing modes immediate direct extended indexed (no offset) indexed (8-bit offset) indexed (16-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles load a from memory lda a6 2 2 b6 2 3 c6 3 4 f6 1 3 e6 2 4 d6 3 5 load x from memory ldx ae 2 2 be 2 3 ce 3 4 fe 1 3 ee 2 4 de 3 5 store a in memory sta b724c735f714e725d736 store x in memory stx bf24cf35ff14ef25df36 add memory to a addab22bb23cb34fb13eb24db35 add memory and carry to a adca922b923c934f913e924d935 subtract memory suba02 2b02 3c03 4f01 3e02 4d03 5 subtract memory from a with borrow sbca22 2b22 3c23 4f21 3e22 4d23 5 and memory with a anda422b423c434f413e424d435 or memory with a oraaa22ba23ca34fa13ea24da35 exclusive or memory with a eora822b823c834f813e824d835 arithmetic compare a with memory cmpa12 2b12 3c13 4f11 3e12 4d13 5 arithmetic compare x with memory cpxa32 2b32 3c33 4f31 3e32 4d33 5 bit test memory with a (logical compare) bit a52 2b52 3c53 4f51 3e52 4d53 5 jump unconditional jmp bc22cc33fc12ec23dc34 jump to subroutine jsr bd25cd36fd15ed26dd37 115
freescale 10-6 mc68HC05B6 rev. 4.1 cpu core and instruction set 10 table 10-3 branch instructions relative addressing mode function mnemonic opcode # bytes # cycles branch always bra 20 2 3 branch never brn 21 2 3 branch if higher bhi 22 2 3 branch if lower or same bls 23 2 3 branch if carry clear bcc 24 2 3 (branch if higher or same) (bhs) 24 2 3 branch if carry set bcs 25 2 3 (branch if lower) (blo) 25 2 3 branch if not equal bne 26 2 3 branch if equal beq 27 2 3 branch if half carry clear bhcc 28 2 3 branch if half carry set bhcs 29 2 3 branch if plus bpl 2a 2 3 branch if minus bmi 2b 2 3 branch if interrupt mask bit is clear bmc 2c 2 3 branch if interrupt mask bit is set bms 2d 2 3 branch if interrupt line is low bil 2e 2 3 branch if interrupt line is high bih 2f 2 3 branch to subroutine bsr ad 2 6 table 10-4 bit manipulation instructions addressing modes bit set/clear bit test and branch function mnemonic opcode # bytes # cycles opcode # bytes # cycles branch if bit n is set brset n (n=0?7) 2?n 3 5 branch if bit n is clear brclr n (n=0?7) 01+2?n 3 5 set bit n bset n (n=0?7) 10+2?n 2 5 clear bit n bclr n (n=0?7) 11+2?n 2 5 115
mc68HC05B6 rev. 4.1 freescale 10-7 cpu core and instruction set 10 table 10-5 read/modify/write instructions addressing modes inherent (a) inherent (x) direct indexed (no offset) indexed (8-bit offset) function mnemonic opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles opcode # bytes # cycles increment inc 4c1 35c1 33c2 57c1 56c2 6 decrement dec4a1 35a1 33a2 57a1 56a2 6 clear clr4f1 35f1 33f2 57f1 56f2 6 complement com431 3531 3332 5731 5632 6 negate (two?s complement) neg 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6 rotate left through carry rol 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6 rotate right through carry ror461 3561 3362 5761 5662 6 logical shift left lsl 481 3581 3382 5781 5682 6 logical shift right lsr 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6 arithmetic shift right asr 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6 test for negative or zero tst4d1 35d1 33d2 47d1 46d2 5 multiply mul 42 1 11 table 10-6 control instructions inherent addressing mode function mnemonic opcode # bytes # cycles transfer a to x tax 97 1 2 transfer x to a txa 9f 1 2 set carry bit sec 99 1 2 clear carry bit clc 98 1 2 set interrupt mask bit sei 9b 1 2 clear interrupt mask bit cli 9a 1 2 software interrupt swi 83 1 10 return from subroutine rts 81 1 6 return from interrupt rti 80 1 9 reset stack pointer rsp 9c 1 2 no-operation nop 9d 1 2 stop stop 8e 1 2 wait wait 8f 1 2 115
freescale 10-8 mc68HC05B6 rev. 4.1 cpu core and instruction set 10 table 10-7 instruction set (1 of 2) mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c adc t ? ttt add t ? ttt and ??tt? asl ? ? ttt asr ? ? ttt bcc ????? bclr ????? bcs ????? beq ????? bhcc ????? bhcs ????? bhi ????? bhs ????? bih ????? bil ????? bit ??tt? blo ????? bls ????? bmc ????? bmi ????? bms ????? bne ????? bpl ????? bra ????? brn ????? brclr ????t brset ????t bset ????? bsr ????? clc ????0 cli ?0??? clr ??01? cmp ? ? ttt condition code symbols h half carry (from bit 3) t tested and set if true, cleared otherwise i interrupt mask ? not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative 115
mc68HC05B6 rev. 4.1 freescale 10-9 cpu core and instruction set 10 table 10-8 instruction set (2 of 2) mnemonic addressing modes condition codes inh imm dir ext rel ix ix1 ix2 bsc btb h i n z c com ??tt1 cpx ??ttt dec ??tt? eor ??tt? inc ??tt? jmp ????? jsr ????? lda ??tt? ldx ??tt? lsl ??ttt lsr ??0tt mul 0???0 neg ??ttt nop ????? ora ??tt? rol ??ttt ror ??ttt rsp ????? rti ????? rts ????? sbc ??ttt sec ????1 sei ?1??? sta ??tt? stop ?0??? stx ??tt? sub ??ttt swi ?1??? tax ????? tst ??tt? txa ????? wait ?0??? condition code symbols h half carry (from bit 3) t tested and set if true, cleared otherwise i interrupt mask ? not affected n negate (sign bit) ? load ccr from stack z zero 0 cleared c carry/borrow 1 set not implemented address mode abbreviations bsc bit set/clear imm immediate btb bit test & branch ix indexed (no offset) dir direct ix1 indexed, 1 byte offset ext extended ix2 indexed, 2 byte offset inh inherent rel relative 115
freescale 10-10 mc68HC05B6 rev. 4.1 cpu core and instruction set 10 table 10-9 m68hc05 opcode map bit manipulation branch read/modify/write control register/memory btb bsc rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix high 0123456789abcdef high low 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 low 0 0000 553533659 234543 0 0000 brset0 bset0 bra neg nega negx neg neg rti sub sub sub sub sub sub 3btb2bsc2rel2dir1inh1inh2 ix11 ix1inh 2imm2 dir3ext3 ix22 ix11 ix 1 0001 553 6 234543 1 0001 brclr0 bclr0 brn rts cmpcmpcmpcmpcmpcmp 3btb2bsc2rel 1inh 2imm2 dir3ext3 ix22 ix11 ix 2 0010 553 11 234543 2 0010 brset1 bset1 bhi mul sbc sbc sbc sbc sbc sbc 3btb2bsc2rel 1inh 2imm2 dir3ext3 ix22 ix11 ix 3 0011 5535336510 234543 3 0011 brclr1 bclr1 bls com coma comx com com swi cpxcpxcpxcpxcpxcpx 3btb2bsc2rel2dir1inh1inh2 ix11 ix1inh 2imm2 dir3ext3 ix22 ix11 ix 4 0100 55353365 234543 4 0100 brset2 bset2 bcc lsr lsra lsrx lsr lsr and and and and and and 3btb2bsc2rel2dir1inh1inh2 ix11 ix 2imm2 dir3ext3 ix22 ix11 ix 5 0101 553 234543 5 0101 brclr2 bclr2 bcs bitbitbitbitbitbit 3btb2bsc2rel 2imm2 dir3ext3 ix22 ix11 ix 6 0110 55353365 234543 6 0110 brset3 bset3 bne ror rora rorx ror ror lda lda lda lda lda lda 3btb2bsc2rel2dir1inh1inh2 ix11 ix 2imm2 dir3ext3 ix22 ix11 ix 7 0111 55353365 2 45654 7 0111 brclr3 bclr3 beq asr asra asrx asr asr tax sta sta sta sta sta 3btb2bsc2rel2dir1inh1inh2 ix11 ix 1inh 2 dir 3 ext 3 ix2 2 ix1 1 ix 8 1000 55353365 2234543 8 1000 brset4 bset4 bhcc lsl lsla lslx lsl lsl clc eor eor eor eor eor eor 3btb2bsc2rel2dir1inh1inh2 ix11 ix 1 inh2imm2 dir3ext3 ix22 ix11 ix 9 1001 55353365 2234543 9 1001 brclr4 bclr4 bhcs rol rola rolx rol rol sec adc adc adc adc adc adc 3btb2bsc2rel2dir1inh1inh2 ix11 ix 1 inh2imm2 dir3ext3 ix22 ix11 ix a 1010 55353365 2234543 a 1010 brset5 bset5 bpl dec deca decx dec dec cli ora ora ora ora ora ora 3btb2bsc2rel2dir1inh1inh2 ix11 ix 1 inh2imm2 dir3ext3 ix22 ix11 ix b 1011 553 2234543 b 1011 brclr5 bclr5 bmi sei add add add add add add 3btb2bsc2rel 1 inh2imm2 dir3ext3 ix22 ix11 ix c 1100 55353365 2 23432 c 1100 brset6 bset6 bmc inc inca incx inc inc rsp jmp jmp jmp jmp jmp 3btb2bsc2rel2dir1inh1inh2 ix11 ix 1inh 2 dir 3 ext 3 ix2 2 ix1 1 ix d 1101 55343354 2656765 d 1101 brclr6 bclr6 bms tst tsta tstx tst tst nop bsr jsr jsr jsr jsr jsr 3btb2bsc2rel2dir1inh1inh2 ix11 ix 1 inh 2 rel 2 dir 3 ext 3 ix2 2 ix1 1 ix e 1110 553 2 234543 e 1110 brset7 bset7 bil stop ldx ldx ldx ldx ldx ldx 3btb2bsc2rel 1inh 2imm2 dir3ext3 ix22 ix11 ix f 1111 5535336522 45654 f 1111 brclr7 bclr7 bih clr clra clrx clr clr wait txa stx stx stx stx stx 3btb2bsc2rel2dir1inh1inh2 ix11 ix1inh1inh 2 dir 3 ext 3 ix2 2 ix1 1 ix f 1111 3 0 0000 sub 1ix opcode in hexadecimal opcode in binary address mode cycles bytes mnemonic legend abbreviations for address modes and registers bsc btb dir ext inh imm ix ix1 ix2 rel a x bit set/clear bit test and branch direct extended inherent immediate indexed (no offset) indexed, 1 byte (8-bit) offset indexed, 2 byte (16-bit) offset relative accumulator index register not implemented 115
mc68HC05B6 rev. 4.1 freescale 10-11 cpu core and instruction set 10 10.3 addressing modes ten different addressing modes provide programmer s with the flexibility to optimize their code for all situations. the various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the memory space. short indexed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. short absolute (direct) and long absolute (extended) addressing are also included. one or two byte direct addressing instructions ac cess all data bytes in most applications. extended addressing permits jump instructions to reach all memory locations. the term ?effective address? (ea) is used in describing the various addressing modes. the effective address is defined as the address from wh ich the argument for an instruction is fetched or stored. the ten addressing modes of the processor are described below. parentheses are used to indicate ?contents of? the location or register referred to. for example, (pc) indicates the contents of the location pointed to by the pc (p rogram counter). an arrow indicates ?is replaced by? and a colon indicates concatenation of two bytes. for additional details and graphical illustrations, refer to the m6805 hmos/m146805 cmos family microcomputer/ microprocessor user's manual or to the m68hc05 applications guide . 10.3.1 inherent in the inherent addressing mode, all the info rmation necessary to execute the instruction is contained in the opcode. operations specifying on ly the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. these instructions are one byte long. 10.3.2 immediate in the immediate addressing mode, the operand is contained in the byte immediately following the opcode. the immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). ea = pc+1; pc pc+2 10.3.3 direct in the direct addressing mode, the effective addre ss of the argument is contained in a single byte following the opcode byte. direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. ea = (pc+1); pc pc+2 address bus high 0; address bus low (pc+1) 115
freescale 10-12 mc68HC05B6 rev. 4.1 cpu core and instruction set 10 10.3.4 extended in the extended addressing mode, the effective addr ess of the argument is contained in the two bytes following the opcode byte. instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. when using the freescale assembler, the user need not specify whether an instruction uses direct or extended addressing. the assembler automatically sele cts the short form of the instruction. ea = (pc+1):(pc+2); pc pc+3 address bus high (pc+1); address bus low (pc+2) 10.3.5 indexed, no offset in the indexed, no offset addressing mode, the ef fective address of the argument is contained in the 8-bit index register. this addressing mode can access the first 256 memory locations. these instructions are only one byte long. this mode is often used to move a pointer through a table or to hold the address of a frequently referenced ram or i/o location. ea = x; pc pc+1 address bus high 0; address bus low x 10.3.6 indexed, 8-bit offset in the indexed, 8-bit offset addressing mode, t he effective address is the sum of the contents of the unsigned 8-bit index register and the unsig ned byte following the opcode. therefore the operand can be located anywhere within the lowest 511 memory locations. this addressing mode is useful for selecting the mth element in an n element table. ea = x+(pc+1); pc pc+2 address bus high k; address bus low x+(pc+1) where k = the carry from the addition of x and (pc+1) 10.3.7 indexed, 16-bit offset in the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two un signed bytes following the opcode. this address mode can be used in a manner similar to indexed, 8- bit offset except that th is three-byte instruction allows tables to be anywhere in memory. as with direct and extended addressing, the freescale assembler determines the shortest form of indexed addressing. ea = x+[(pc+1):(pc+2)]; pc pc+3 address bus high (pc+1)+k; address bus low x+(pc+2) where k = the carry from the addition of x and (pc+2) 115
mc68HC05B6 rev. 4.1 freescale 10-13 cpu core and instruction set 10 10.3.8 relative the relative addressing mode is only used in branch instructions. in relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the pc if, and only if, the branch conditions are true. otherwise, cont rol proceeds to the next instruction. the span of relative addressing is from ?126 to +129 from the opcode address. the programmer need not calculate the offset when using the freescale assemb ler, since it calculates the proper offset and checks to see that it is wit hin the span of the branch. ea = pc+2+(pc+1); pc ea if branch taken; otherwise ea = pc pc+2 10.3.9 bit set/clear in the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. the byte following the opcode specifies the address of the byte in which the specified bit is to be set or cleared. any read/write bit in the first 256 locations of memory, including i/o, can be selectively set or cleared with a single two-byte instruction. ea = (pc+1); pc pc+2 address bus high 0; address bus low (pc+1) 10.3.10 bit test and branch the bit test and branch addressing mode is a combination of direct addressing and relative addressing. the bit to be tested and its condition (set or clear) is included in the opcode. the address of the byte to be tested is in the si ngle byte immediately following the opcode byte (ea1). the signed relative 8-bit offset in the third byte ( ea2) is added to the pc if the specified bit is set or cleared in the specified memory location. this single three-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. the span of branch is from ?125 to +130 from the op code address. the state of the tested bit is also transferred to the carry bit of the condition code register. ea1 = (pc+1); pc pc+2 address bus high 0; address bus low (pc+1) ea2 = pc+3+(pc+2); pc ea2 if branch taken; otherwise pc pc+3 115
freescale 10-14 mc68HC05B6 rev. 4.1 cpu core and instruction set 10 this page left bl ank intentionally 115
mc68HC05B6 rev. 4.1 freescale 11-1 electrical specifications 11 11 electrical specifications this section contains the electrical specifications and associated timing information for the mc68HC05B6. 11.1 absolute maximum ratings note: this device contains circuitry designed to protect against damage due to high electrostatic voltages or electric fields. however, it is recommended that normal precautions be taken to avoid the application of any voltages higher than those given in the maximum ratings table to this high impedance circuit. for maximum reliability all unused inputs should be tied to either v ss or v dd . table 11-1 absolute maximum ratings rating symbol value unit supply voltage (1) (1) all voltages are with respect to v ss . v dd ? 0.5 to +7.0 v input voltage (except v pp1 )v in v ss ? 0.5 to v dd + 0.5 v input voltage ? self-check mode (irq pin only) v in v ss ? 0.5 to 2v dd + 0.5 v operating temperature range ? standard (mc68HC05B6) ? extended (mc68HC05B6c) ? automotive (mc68HC05B6m) t a t l to t h 0 to +70 ?40 to +85 ?40 to +125 c storage temperature range t stg ? 65 to +150 c current drain per pin (excluding vdd and vss) (2) ? source ? sink (2) maximum current drain per pin is for one pin at a time, limited by an external resistor. i d i s 25 45 ma ma 129 130 131 132 133
freescale 11-2 mc68HC05B6 rev. 4.1 electrical specifications 11 11.2 dc electrical characteristics table 11-2 dc electrical characteristics for 5v operation (v dd = 5 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic (1) (1) all i dd measurements taken with suitable decoupling capacitor s across the power supply to suppress the transient switching currents inherent in cmos designs (see section 2). symbol min typ (2) (2) typical values are at mid poi nt of voltage range and at 25 c only. max unit output voltage i load = ? 10 a i load = +10 a v oh v ol v dd ? 0.1 ? ? ? ? 0.1 v output high voltage (i load = 0.8ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2 output high voltage (i load = 1.6ma) tdo, sclk, plma, plmb v oh v oh v dd ? 0.8 v dd ? 0.8 v dd ? 0.4 v dd ? 0.4 ? ? v output low voltage (i load = 1.6ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 1.6ma) reset v ol v ol ?0.1 0.4 0.4 1 v input high voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset , tcap1, tcap2, rdi v ih 0.7v dd ?v dd v input low voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset ,tcap1, tcap2, rdi v il v ss ?0.2v dd v supply current (3) run (sm = 0) (see figure 11-1 ) run (sm = 1) (see figure 11-2 ) wait (sm = 0) (see figure 11-3 ) wait (sm = 1) (see figure 11-4 ) stop 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 105 (extended) ? 40 to 125 (automotive) (3) run and wait i dd : measured using an external square-wave clock source (f osc = 4.2mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all ports configured as inputs; v il = 0.2 v and v ih =v dd ? 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance. i dd ? ? ? ? ? ? ? ? 3.5 0.5 1 0.35 2 ? ? ? 6 1.5 2 1 10 20 60 60 ma ma ma ma a a a a high-z leakage current pa0?7, pb0?7, pc0?7, tdo, reset , sclk i il ? 0.2 1 a input current (0 to 70) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ? 0.2 0.2 1 1 ma input current (? 40 to 125) irq , osc1, tcap1, tcap2, rdi, i in ?? 5 a capacitance ports (as input or output), reset , tdo, sclk irq , tcap1, tcap2, osc1, rdi pd0/an0?pd7/an7 (a/d off) pd0/an0?pd7/an7 (a/d on) c out c in c in c in ? ? ? ? ? ? 12 22 12 8 ? ? pf pf pf pf 134 135 136 137 138
mc68HC05B6 rev. 4.1 freescale 11-3 electrical specifications 11 11.2.1 i dd trends for 5v operation for the examples below, typical values are at the mid-point of the voltage range and at a temperature of 25 c only. figure 11-1 run i dd vs internal operating frequency (4.5v, 5.5v) figure 11-2 run i dd (sm = 1) vs internal operating frequency (4.5v, 5.5v) figure 11-3 wait i dd vs internal operating frequency (4.5v, 5.5v) 8 7 6 5 4 3 2 1 0 00.511.522.533.54 i dd (ma) internal operating frequency (mhz) 5.5v 4.5v 1.2 0 00.511.522.533.54 i dd (ma) internal operating frequency (mhz) 5.5v 4.5v 1 0.8 0.6 0.4 0.2 2.5 0 00.511.522.533.54 i dd (ma) internal operating frequency (mhz) 5.5v 4.5v 2 1.5 1 0.5 139 140
freescale 11-4 mc68HC05B6 rev. 4.1 electrical specifications 11 figure 11-4 wait i dd (sm = 1) vs internal operating frequency (4.5v, 5.5v) figure 11-5 increase in i dd vs frequency for a/d, sci systems active, vdd = 5.5v figure 11-6 i dd vs mode vs internal operating frequency, v dd = 5.5v 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 00.511.522.533.54 i dd (ma) internal operating frequency (mhz) 5.5v 4.5v 0.9 1.4 1.2 1 0.8 0.6 0.4 0.2 0 00.511.522.53 i dd (ma) internal operating frequency (mhz) a/d + sci a/d 1.6 sci 8 7 6 5 4 3 2 1 0 00.511.522.533.54 i dd (ma) internal operating frequency (mhz) wait i dd (sm = 1) run i dd wait i dd run i dd (sm = 1)
mc68HC05B6 rev. 4.1 freescale 11-5 electrical specifications 11 table 11-3 dc electrical characteristics for 3.3v operation (v dd = 3.3vdc 10%, v ss = 0vdc, t a = t l to t h ) characteristic (1) symbol min typ (2) max unit output voltage i load = ? 10 a i load = +10 a v oh v ol v dd ? 0.1 ? ? ? ? 0.1 v output high voltage (i load = 0.2ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2 output high voltage (i load = 0.4ma) tdo, sclk, plma, plmb v oh v oh v dd ? 0.3 v dd ? 0.3 v dd ? 0.1 v dd ? 0.1 ? ? v output low voltage (i load = 0.4ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 0.4ma) reset v ol v ol ?0.1 0.2 0.3 0.6 v input high voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset , tcap1, tcap2, rdi v ih 0.7v dd ?v dd v input low voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset , tcap1, tcap2, rdi v il v ss ?0.2v dd v supply current (3) run (sm = 0) (see figure 11-1 ) run (sm = 1) (see figure 11-2 ) wait (sm = 0) (see figure 11-3 ) wait (sm = 1) (see figure 11-4 ) stop 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 105 (extended) ? 40 to 125 (automotive) i dd ? ? ? ? ? ? ? ? 1.2 0.2 0.4 0.15 1 ? ? ? 3 1 1.5 0.5 10 10 40 40 ma ma ma ma a a a a high-z leakage current pa0?7, pb0?7, pc0?7, tdo, reset , sclk i il ? 0.2 1 a input current (0 to 70) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ? 0.2 0.2 1 1 a input current (? 40 to 125) irq , osc1, tcap1, tcap2, rdi, i in ?? 5 a capacitance ports (as input or output), reset , tdo, sclk irq , tcap1, tcap2, osc1, rdi pd0/an0?pd7/an7 (a/d off) pd0/an0?pd7/an7 (a/d on) c out c in c in c in ? ? ? ? ? ? 12 22 12 8 ? ? pf pf pf pf (1) all i dd measurements taken with suitable decoupling capa citors across the power supply to suppress the transient switching currents inherent in cmos designs (see section 2). (2) typical values are at mid point of voltage range and at 25 c only. (3) run and wait i dd : measured using an external square-wave clock source (f osc = 2.0mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all ports configured as inputs; v il = 0.2 v and v ih =v dd ? 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance.
freescale 11-6 mc68HC05B6 rev. 4.1 electrical specifications 11 11.2.2 i dd trends for 3.3v operation for the examples below, typical values are at the mid-point of the voltage range and at a temperature of 25 c only. figure 11-7 run i dd vs internal operating frequency (3 v, 3.6v) figure 11-8 run i dd (sm = 1) vs internal operating frequency (3v,3.6v) figure 11-9 wait i dd vs internal operating frequency (3v, 3.6v) 2.5 0 00.511.522.5 i dd (ma) internal operating frequency (mhz) 3.6v 3.0v 2 1.5 1 0.5 0.6 0 00.511.522.5 i dd (ma) internal operating frequency (mhz) 3.6v 3.0v 0.5 0.4 0.3 0.2 0.1 1.2 0 00.511.522.5 i dd (ma) internal operating frequency (mhz) 3.6v 3.0v 1 0.8 0.6 0.4 0.2
mc68HC05B6 rev. 4.1 freescale 11-7 electrical specifications 11 figure 11-10 wait i dd (sm = 1) vs internal operating frequency (3v, 3.6v) figure 11-11 increase in i dd vs frequency for a/d, sci systems active, v dd = 3.6v figure 11-12 i dd vs mode vs internal operating frequency, v dd = 3.6v 0.5 0 00.511.522.5 i dd (ma) internal operating frequency (mhz) 3.6v 3.0v 0.4 0.3 0.2 0.1 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 00.511.522.5 i dd (ma) internal operating frequency (mhz) a/d sci a/d + sci 2.5 2 1.5 1 0.5 0 00.511.522.5 i dd (ma) internal operating frequency (mhz) run i dd wait i dd run i dd (sm=1) wait i dd (sm=1)
freescale 11-8 mc68HC05B6 rev. 4.1 electrical specifications 11 11.3 a/d converte r characteristics table 11-4 a/d characteristics for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 ? bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) ? 0.5 lsb quantization error uncertainty due to converter resolution ? 0.5 lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors ? 1lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss ? 0.1 v rh v ? v r (1) (1) performance verified down to 2.5v ? vr, but accuracy is tested and guaranteed at ? vr = 5v 10%. minimum difference between v rh and v rl 3?v conversion time total time to perfor m a single analog to digital conversion a. external clock (osc1, osc2) b. internal rc oscillator ? ? 32 32 t cyc s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conv ersion result when v in = v rl 00 ? hex full scale reading conversion result when v in = v rh ?ffhex sample acquisition time analog input acquisition sampling a. external clock (osc1, osc2) b. internal rc oscillator (2) (2) source impedances greater than 10k ? will adversely affect internal charging time during input sampling. ? ? 12 12 t cyc s sample/hold capacitance input capacitance on pd0/an0?pd7/an7 ? 12 pf input leakage (3) (3) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input current to a/d channel will be dependent on external source impedance (see figure 8-2 ). input leakage on a/d pins pd0/an0?pd7/an7, vrl, vrh ? 1 a
mc68HC05B6 rev. 4.1 freescale 11-9 electrical specifications 11 table 11-5 a/d characteristics for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 ? bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) ? 1lsb quantization error uncertainty due to converter resolution ? 1lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors ? 2lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss ? 0.1 v rh v ? v r minimum difference between v rh and v rl 3?v conversion time total time to perform a single analog to digital conversion internal rc oscillator ? 32 s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conversion result when v in = v rl 00 ? hex full scale reading conversion result when v in = v rh ?ffhex sample acquisition time analog input acquisition sampling internal rc oscillator (1) ?12 s sample/hold capacitance input capacitance on pd0/an0?pd7/an7 ? 12 pf input leakage (2) input leakage on a/d pins pd0/an0?pd7/an7, vrl, vrh ? 1 a (1) source impedances greater than 10k ? will adversely affect internal charging time during input sampling. (2) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input cu rrent to a/d channel w ill be dependent on external source impedance (see figure 8-2 ).
freescale 11-10 mc68HC05B6 rev. 4.1 electrical specifications 11 11.4 control timing table 11-6 control timing for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc ? dc 4.2 4.2 mhz mhz internal operating frequency (f osc /2) using crystal using external clock f op f op dc dc 2.1 2.1 mhz mhz cycle time (see figure 9-1 )t cyc 476 ? ns crystal oscillator start-up time (see figure 9-1 )t oxov ?100ms stop recovery start-up time (crystal oscillator) t ilch 100 ms rc oscillator stabilization time t adrc 5 s a/d converter stabilization time t adon 500 s external reset input pulse width t rl 1.5 ? t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 ? ? t cyc t cyc watchdog reset output pulse width t dogl 1.5 ? t cyc watchdog time-out t dog 6144 7168 t cyc eeprom byte erase time 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 125 (automotive) t era t era t era 10 10 10 ? ? ? ms ms ms eeprom byte program time (1) 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 125 (automotive) (1) for bus frequencies less than 2 mhz, the internal rc oscillator should be used when programming the eeprom. t prog t prog t prog 10 10 20 ? ? ? ms ms ms timer (see figure 11-13 ) resolution (2) input capture pulse width input capture pulse period (2) since a 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. t resl t th , t tl t tltl 4 125 ? (3) (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . ? ? ? t cyc ns t cyc interrupt pulse widt h (edge-triggered) t ilih 125 ? ns interrupt pulse period t ilil ? (4) (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . ?t cyc osc1 pulse width (5) (5) t oh and t ol should not total less than 238ns. t oh , t ol 90 ? ns write/erase endurance (6)(7) (6) at a temperature of 85 c ? 10000 cycles data retention (6)(7) (7) refer to reliability monitor report (current quar terly issue) for current failure rate information. ?10years
mc68HC05B6 rev. 4.1 freescale 11-11 electrical specifications 11 table 11-7 control timing for 3.3v operation (v dd = 3.3vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc ? dc 2.0 2.0 mhz mhz internal operating frequency (f osc /2) using crystal using external clock f op f op ? dc 1.0 1.0 mhz mhz cycle time (see figure 9-1 )t cyc 1000 ? ns crystal oscillator start-up time (see figure 9-1 )t oxov ? 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms rc oscillator stabilization time t adrc 5 s a/d converter stabilization time t adon 500 s external reset input pulse width t rl 1.5 ? t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 ? ? t cyc t cyc watchdog reset output pulse width t dogl 1.5 ? t cyc watchdog time-out t dog 6144 7168 t cyc eeprom byte erase time 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 125 (automotive) t era t era t era 30 30 30 ? ? ? ms ms ms eeprom byte program time (1) 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 125 (automotive) t prog t prog t prog 30 30 30 ? ? ? ms ms ms timer (see figure 11-13 ) resolution (2) input capture pulse width input capture pulse period t resl t th , t tl t tltl 4 250 ? (3) ? ? ? t cyc ns t cyc interrupt pulse width (edge-triggered) t ilih 250 ? ns interrupt pulse period t ilil ? (4) ?t cyc osc1 pulse width (5) t oh , t ol 200 ? ns write/erase endurance (6)(7) ? 10000 cycles data retention (6)(7) ? 10 years (1) for bus frequencies less than 2 mhz, the inte rnal rc oscillator should be used when programming the eeprom. (2) since a 2-bit prescaler in the time r must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . (5) t oh and t ol should not total less than 500ns. (6) at a temperature of 85 c (7) refer to reliability monitor report (current quar terly issue) for current failure rate information.
freescale 11-12 mc68HC05B6 rev. 4.1 electrical specifications 11 figure 11-13 timer relationship external signal (tcap1, tcap2) t tltl t th t tl
mc68HC05B6 rev. 4.1 freescale 12-1 mechanical data 12 12 mechanical data 12.1 mc68hc05b family pin configurations 12.1.1 52-pin plastic leaded chip carrier (plcc) figure 12-1 52-pin plcc pinout for the mc68HC05B6 pc3 pc4 pc5 pc6 pc7 vss vpp1/nu pb0 pb1 pb2 pb3 pb4 pb5 vrh pd4/an4 vdd pd3/an3 pd2/an2 pd1/an1 pd0/an0 nc/vpp6 osc1 osc2 reset irq plma plmb tcap1 tcap2 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb7 pb6 vrl nc/nu pd5/an5 pd6/an6 pd7/an7 tcmp1 tcmp2 tdo sclk rdi pc0 pc1 pc2/eclk 46 45 44 43 42 41 40 39 38 37 36 35 34 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 7 6 5 4 3 2 52 51 50 49 48 47 device pin 6 pin 15 pin 40 mc68hc05b4 nc nc nu mc68HC05B6 nc nc vpp1 mc68hc05b8 nc nc vpp1 mc68hc05b16 nc nc vpp1 mc68hc05b32 nc nc vpp1 mc68hc705b5 nc vpp6 nu mc68hc705b16 nu vpp6 vpp1 mc68hc705b16n nu vpp6 vpp1 mc68hc705b32 nu vpp6 vpp1 nc = not connected nu = non-user pin (should be tied to v ss in an electrically noisy environment) tpg 141
freescale 12-2 mc68HC05B6 rev. 4.1 mechanical data 12 12.1.2 64-pin quad flat pack (qfp) figure 12-2 64-pin qfp pinout for the mc68HC05B6 nc pb0 nc/nu vpp1/nc 17 18 20 21 22 23 24 25 26 27 29 30 31 32 19 48 47 45 44 43 42 41 40 39 38 37 36 35 34 33 46 pb6 pb7 nc pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 nc tcap2 tcap1 plmb d/a nc pc1 pc0 nc nc nc nc rdi sclk tdo tcmp2 tcmp1 pd7/an7 pd6/an6 pd5/an5 nc nc vrl vrh vdd pd3/an3 pd2/an2 pd1/an1 nc nc nc/vpp6 osc1 osc2 reset irq plma d/a pd4/an4 pc2/eclk pc3 pc5 pc6 pc7 vss pb1 pb2 pb3 pb4 pb5 pc4 1 2 4 5 6 7 8 9 10 11 12 13 14 15 16 3 pd0/an0 28 64 63 61 60 59 58 56 55 54 53 52 51 50 49 62 57 device pin 27 pin 55 pin 57 mc68hc05b4 nc nc nc mc68HC05B6 mc68hc05b8 mc68hc05b16 mc68hc05b32 nc nc vpp1 mc68hc705b5 not available in this package mc68hc705b16 vpp6 nu vpp1 mc68hc705b16n vpp6 nu vpp1 mc68hc705b32 vpp6 nc vpp1 nc = not connected nu = non-user pin (should be tied to v ss in an electrically noisy environment) tpg 142
mc68HC05B6 rev. 4.1 freescale 12-3 mechanical data 12 12.1.3 56-pin shrink dual in line package (sdip) figure 12-3 56-pin sdip pinout for the mc68HC05B6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 tcmp1 pd7 pd6 pd5 nc nc/nu nc vrl vrh pd4 vdd pd3 pd2 pd1 pd0 nc/vpp6 osc1 osc2 reset irq plma 22 23 24 25 26 27 28 56 tcmp2 tdo sclk rdi pc0 pc1 nc pc2 pc3 pc4 pc5 pc6 pc7 vss vpp1/nc pb0 pb1 pb2 pb3 pb4 pb5 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 plmb tcap1 tcap2 pa7 pa6 pa5 pa4 nc pb6 pb7 pa0 pa1 pa2 pa3 device pin 6 pin 16 pin 42 mc68hc05b4 nc nc nc mc68HC05B6 nc nc vpp1 mc68hc05b8 nc nc vpp1 mc68hc05b16 nc nc vpp1 mc68hc05b32 nc nc vpp1 mc68hc705b5 nc vpp6 nc mc68hc705b16 not available in this package mc68hc705b16n contact sales mc68hc705b32 nu vpp6 vpp1 nc = not connected nu = non-user pin (should be tied to v ss in an electrically noisy environment) tpg 143
freescale 12-4 mc68HC05B6 rev. 4.1 mechanical data 12 12.2 mc68HC05B6 me chanical dimensions 12.2.1 52-pin plastic leaded chip carrier (plcc) figure 12-4 52-pin plcc mechanical dimensions ?l? ?m? ?p? ?n? pin 1 pin 52 v w y brk z r a c j e g g1 u b g1 z1 x 0.10 ?t? seating plane 0.18 t n ?p l ?m m s s s s case no. 778-02 52 lead plcc w/o pedestal dim. min. max. notes dim. min. max. a 19.94 20.19 1. datums ?l?, ?m?, ?n? and ?p? are determined where top of lead shoulder exits plastic body at mould parting line. 2. dimension g1, true position to be measured at datum ?t? (seating plane). 3. dimensions r and u do not incl ude mould protrusion. allowable mould protrusion is 0.25mm per side. 4. dimensions and tolerancing per ansi y 14.5m, 1982. 5. all dimensions in mm. u 19.05 19.20 b 19.94 20.19 v 1.07 1.21 c 4.20 4.57 w 1.07 1.21 e 2.29 2.79 x 1.07 1.42 f 0.33 0.48 y ? 0.50 g1.27 bsc z2 10 h 0.66 0.81 g1 18.04 18.54 j0.51? k11.02? k0.64? z1 2 10 r 19.05 19.20 0.18 t l ?m n ?p m s s s s 0.18 t l ?m n ?p m s s s s 0.18 t n ?p l ?m m s s s s 0.25 t l ?m n ?p s s s s s tpg 144
mc68HC05B6 rev. 4.1 freescale 12-5 mechanical data 12 12.2.2 64-pin quad flat pack (qfp) figure 12-5 64-pin qfp mechanical dimensions 64 lead qfp 0.20 m ca ? b s d s l 33 48 16 1 32 17 49 64 - b - b v 0.05 a ? b - d - a s 0.20 m ha ? b s d s l - a - detail ?a? b b - a, b, d - p detail ?a? f n j d section b?b base metal g h e c -c- m detail ?c? m -h- datum plane seating plane u t r q k w x dim. min. max. notes dim. min. max. a 13.90 14.10 1. datum plane ?h? is located at botto m of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 2. datums a?b and ?d to be determined at datum plane ?h?. 3. dimensions s and v to be determined at seating plane ?c?. 4. dimensions a and b do not include mould protrusion. allowable mould protrusion is 0.25mm pe r side. dimensions a and b do include mould mismatch and are determined at datum plane ?h?. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 tota l in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. 6. dimensions and tolerancing per ansi y 14.5m, 1982. 7. all dimensions in mm. m5 10 b 13.90 14.10 n 0.130 0.170 c 2.067 2.457 p 0.40 bsc d0.300.45 q 2 8 e 2.00 2.40 r 0.13 0.30 f 0.30 ? s 16.20 16.60 g 0.80 bsc t 0.20 ref h 0.067 0.250 u 9 15 j 0.130 0.230 v 16.20 16.60 k 0.50 0.66 w 0.042 nom l 12.00 ref x 1.10 1.30 0.20 m ca ? b s d s 0.05 a ? b 0.20 m ha ? b s d s 0.20 m ca ? b s d s case no. 840c tpg 145
freescale 12-6 mc68HC05B6 rev. 4.1 mechanical data 12 12.2.3 56-pin shrink dual in line package (sdip) figure 12-6 56-pin sdip mechanical dimensions 128 56 29 - a - n g d f l m plane seating c dim. min. max. notes dim. min. max. a 51.69 52.45 1. due to space limitations, this case shall be represented by a general case outline, rather than one showing all the leads. 2. dimensions and tolerancing per ansi y 14.5 1982. 3. all dimensions in mm. 4. dimension l to centre of lead when formed parallel. 5. dimensions a and b do not include mould flash. allowable mould flash is 0.25 mm. h 7.62 bsc b 13.72 14.22 j 0.20 0.38 c 3.94 5.08 k 2.92 3.43 d 0.36 0.56 l 15.24 bsc e0.89 bsc m0 15 f 0.81 1.17 n 0.51 1.02 g 1.778 bsc case no. 859-01 56 lead sdip - b - h k - t - 0.25 t a m s 0.25 t b m s j e tpg 146
mc68HC05B6 rev. 4.1 freescale 13-1 ordering information 13 13 ordering information this section describes the information needed to order the mc68HC05B6 an d other family members. to initiate a rom pattern for the mcu, it is necessa ry to contact your local field service office, local sales person or freescale representative. please not e that you will need to supply details such as: mask option selections; temperature range; oscill ator frequency; package type; electrical test requirements; and device marking details so that an order can be processed, and a customer specific part number allocated. refer to ta b l e 1 3 - 1 for appropriate part numbers. the part number consists of the device title plus the appropria te suffix. for example, the mc68HC05B6 in 52-pin plcc package at ?40 to +85 c would be ordered as: mc68HC05B6cfn. table 13-1 mc order numbers device title package type suffix 0 to 70 c suffix -40 to +85 c suffix -40 to +105 c suffix -40 to +125 c mc68HC05B6 52-pin plcc fn cfn vfn mfn 64-pin qfp fu cfu vfu mfu 56-pin sdip b cb vb mb mc68hc05b4 52-pin plcc fn cfn vfn mfn 64-pin qfp fu cfu vfu mfu 56-pin sdip b cb vb mb mc68hc05b8 52-pin plcc fn cfn vfn mfn 64-pin qfp fu cfu vfu mfu 56-pin sdip b cb vb mb mc68hc05b16 52-pin plcc fn cfn vfn mfn 64-pin qfp fu cfu vfu mfu 56-pin sdip b cb vb mb mc68hc05b32 52-pin plcc fn cfn n/a n/a 64-pin qfp fu cfu n/a n/a 56-pin sdip b contact sales n/a n/a mc68hc705b5 52-pin plcc fn cfn vfn mfn 56-pin sdip b cb vb mb mc68hc705b16 52-pin plcc fn cfn vfn mfn 64-pin qfp fu cfu vfu mfu mc68hc705b16n 52-pin plcc fn cfn vfn mfn 64-pin qfp fu cfu vfu mfu 56-pin sdip contact sales mc68hc705b32 52-pin plcc fn cfn n/a n/a 64-pin qfp fu cfu n/a n/a 56-pin sdip b cb n/a n/a 147 148
freescale 13-2 mc68HC05B6 rev. 4.1 ordering information 13 13.1 eproms for the mc68HC05B6, an 8 kbyte eprom programmed with the customer?s software (positive logic for address and data) should be submitted for pattern generation. all unused bytes should be programmed to $00. the size of eprom which sh ould be used for all other family members is listed in ta bl e 1 3 - 2 . the eprom should be clearly labelled, placed in a conductive ic carrier and securely packed. 13.2 verification media all original pattern media (eproms) are filed fo r contractual purposes and are not returned. a computer listing of the rom code will be generated and returned with a listing verification form. the listing should be thoroughly checked and the verification form completed, signed and returned to freescale. the signed verification form constitutes the contractual agreement for creation of the custom mask. if desired, freescale will prog ram blank eproms (supplied by the customer) from the data file used to create the custom mask, to aid in the verification process. 13.3 rom verification units (rvu) ten mcus containing the customer?s rom pattern will be provided for program verification. these units will have been made using the custom mask but are for rom verification only. for expediency, they are usually unmarked and are tested only at room temperature (25 c) and at 5 volts. these rvus are included in the mask charge and are not production parts. they are neither backed nor guaranteed by freescale quality assurance. table 13-2 eproms for pattern generation device size of eprom mc68hc05b4 8 kbyte mc68hc05b8 8 kbyte mc68hc05b16 16 kbyte mc68hc05b32 32 kbyte
mc68HC05B6 rev. 4.1 freescale a-1 mc68hc05b4 14 a mc68hc05b4 the mc68hc05b4 is a device similar to the mc68HC05B6, but without eeprom and having a reduced rom size of 4 kbytes. the entire mc68HC05B6 data sheet applies to the mc68hc05b4, with the exceptions outlined in this appendix. a.1 features 4158 bytes user rom (including 14 bytes user vectors) no eeprom high speed version not available section 3.5, ?eeprom?, therefore, does not apply to the mc68hc05b4, and the register at address $07 only allows the user to select whet her or not the eclk should appear at pc2, using bit 3 of $07. all other bits of this register read as ?0?. table a-1 mode of operation selection irq pin tcap1 pin pd3 pd4 mode v ss to v dd v ss to v dd x x single chip 2v dd v dd 0 x self check 2v dd v dd 1 0 serial ram loader 2v dd v dd 1 1 jump to any address 149 150 151 152 153
freescale a-2 mc68HC05B6 rev. 4.1 mc68hc05b4 14 figure a-1 mc68hc05b4 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit programmable timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator 176 bytes ram cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo 2 / 32 plma d/a plmb d/a 8-bit 432 bytes user rom 4158 bytes self check rom (including 14 bytes user vectors) 154 155 156
mc68HC05B6 rev. 4.1 freescale a-3 mc68hc05b4 14 figure a-2 memory map of the mc68hc05b4 user vectors (14 bytes) $1ff2?3 sci timer overflow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $1ff0 stack ram (176 bytes) $02c0 $0200 $1f00 $0050 port a data direction register port b data direction register port c data direction register eeprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f page 0 user rom (48 bytes) self-check rom i (192 bytes) user rom (4096 bytes) self-check rom ii (240 bytes) $0f00 reserved mc68hc05b4 registers $1ff4?5 $1ff6?7 $1ff8?9 $1ffa?b $1ffc?d $1ffe?f
freescale a-4 mc68HC05B6 rev. 4.1 mc68hc05b4 14 table a-2 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 undefined port b data (portb) $0001 undefined port c data (portc) $0002 pc2/ eclk undefined port d data (portd) $0003 pd7/ an7 pd6/ an6 pd5/ an5 pd4/ an4 pd3/ an3 pd2/ an2 pd1/ an1 pd0/ an0 undefined port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eclk control $0007 0 0 0 0 eclk 0 0 0 0000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl uuuu uuuu sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 uuuu uuuu input capture high 1 $0014 undefined input capture low 1 $0015 undefined output compare high 1 $0016 undefined output compare low 1 $0017 undefined timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c undefined input capture low 2 $001d undefined output compare high 2 $001e undefined output compare low 2 $001f undefined (1) this bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent upon t he mask option selected; 1=watchdog enabled, 0=watchdog disabled.
mc68HC05B6 rev. 4.1 freescale a-5 mc68hc05b4 14 a.2 self-check mode the self-check function available on the mc 68hc05b4 provides an internal capability to determine if the device is functional. self-c heck is performed using the circuit shown in figure a-3 . port c pins pc0?pc3 are monitored for the self-check results (light emitting diodes are shown but other devices could be used), and are interpreted as described in ta bl e a - 3 . the self-check mode is entered by applying 2 x v dd dc (via a 4.7k ? resistor) to the irq pin and 5v dc input (via a 4.7k ? resistor) to the tcap1 pin and then depressing the reset switch to execute a reset. after reset, the following tests are performed automatically and once completed they continually repeat. a good device will exhibit flashing leds; a bad device will be indicated by the leds holding at one value. note: self-check code can be obtained from your local freescale representative. i/0 ? functionally exercises ports a, b, c and d ram ? counter test for each ram byte rom ? exclusive or with odd ones parity result timer ? tracks counter registers and checks icf1, icf2, ocf1, ocf2 and tof flags sci ? transmission test; check for rdrf, tdre, tc and fe flags a/d ? check a/d functionality on internal channels: vrl, vrh and (vrl + vrh)/2 plm ? checks the plm basic functionality interrupts ? tests external timer and sci interrupts watchdog? tests the watchdog caution: this document includes descriptions of the various self-check and bootstrap mechanisms that are currently implemented as firmware in the non-user rom areas of the mc68HC05B6 and related devices. as these firmware routines are intended primarily to help freescale?s engineers test the devices, they may be changed or removed at any time. for this reason, freescale recommends the self-check and bootstrap routines are not called from the user software. customers who do call these routines from the user software do so at their own risk.
freescale a-6 mc68HC05B6 rev. 4.1 mc68hc05b4 14 table a-3 mc68hc05b4 self-check results pc3 pc2 pc1 pc0 remarks 1 0 0 1 bad port 0 1 1 0 bad port 1010bad ram 1011bad rom 1100bad timer 1101bad sci 1110bad a/d 0001bad plm 0 0 1 0 bad interrupts 0 0 1 1 bad watchdog flashing good device all others bad device, bad port etc. ?0? indicates led on; ?1? indicates led off
mc68HC05B6 rev. 4.1 freescale a-7 mc68hc05b4 14 figure a-3 mc68hc05b4 self-check schematic diagram 6 40 51 osc1 osc2 irq tcap2 tcmp2 tcap1 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 vrl vss pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 tcmp1 sclk plmb plma tdo rdi vpp1 nc reset nc vrh vdd 18 50 52 20 21 2 3 4 5 9 11 12 13 14 24 25 26 27 28 29 30 31 16 17 19 23 1 22 32 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 41 7 0.01 f 10 nf 47 f 10 m ? 4 mhz 22 pf 4k7 ? 4k7 ? 680 ? 22 pf 4k7 ? 4k7 ? 680 ? 680 ? 680 ? bc239 p1 gnd +5v 2xv dd reset eeprom tested eeprom not tested 15 8 10 note: for the mc68hc05b4, switches on pb5 and pb6 have no effect all resistors are 10 k ? , unless otherwise stated. mc68hc05b4 (52-pin package)
freescale a-8 mc68HC05B6 rev. 4.1 mc68hc05b4 14 this page left bl ank intentionally
mc68HC05B6 rev. 4.1 freescale b-1 mc68hc05b8 14 b mc68hc05b8 the mc68hc05b8 is a device similar to the mc68HC05B6, but with an increased rom size of 7.25 kbytes. the entire mc68HC05B6 data sheet applies to the mc68hc05b8, with the exceptions outlined in this appendix. b.1 features 7230 bytes user rom (including 14 bytes user vectors) high speed version available tpg 157
freescale b-2 mc68HC05B6 rev. 4.1 mc68hc05b8 14 figure b-1 mc68hc05b8 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit programmable timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator 176 bytes ram cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp1 256 bytes eeprom charge pump 2 / 32 plma d/a plmb d/a 8-bit 432 bytes user rom 7230 bytes self check rom (including 14 bytes user vectors) tpg 158
mc68HC05B6 rev. 4.1 freescale b-3 mc68hc05b8 14 figure b-2 memory map of the mc68hc05b8 port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $1ff0 stack ram (176 bytes) $02c0 $0200 $1f00 $0050 port a data direction register port b data direction register port c data direction register eeprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f page 0 user rom (48 bytes) self-check rom i (192 bytes) user rom (7168 bytes) self-check rom ii (240 bytes) $0300 optr (1 byte) non protected (31 bytes) protected (224 bytes) eeprom (256 bytes) $0101 $0120 $0100 options register reserved mc68hc05b8 registers user vectors (14 bytes) $1ff2?3 sci timer overflow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $1ff4?5 $1ff6?7 $1ff8?9 $1ffa?b $1ffc?d $1ffe?f tpg 159
freescale b-4 mc68HC05B6 rev. 4.1 mc68hc05b8 14 table b-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 undefined port b data (portb) $0001 undefined port c data (portc) $0002 pc2/ eclk undefined port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 undefined port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eeprom/eclk control $0007 0 0 0 0 eclk e1era e1lat e1pgm 0000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl undefined sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 undefined input capture high 1 $0014 undefined input capture low 1 $0015 undefined output compare high 1 $0016 undefined output compare low 1 $0017 undefined timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c undefined input capture low 2 $001d undefined output compare high 2 $001e undefined output compare low 2 $001f undefined options (optr) (3) $0100 ee1p sec not affected (1) this bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) this register is implemented in eeprom; theref ore reset has no effect on the individual bits. tpg 160
mc68HC05B6 rev. 4.1 freescale c-1 mc68hc705b5 14 c mc68hc705b5 the mc68hc705b5 is a device similar to the mc68HC05B6, but with the 6 kbytes rom and 256 bytes eeprom replaced by a single eprom array. in addition, t he self-check routines available on the mc68HC05B6 are replaced by bootstrap firmware. the mc68hc705b5 is intended to operate as a one time programmable (otp) vers ion of the mc68HC05B6 without eeprom or the mc68hc05b4, meaning that the application program can never be erased once it has been loaded into the eprom. the entire mc68HC05B6 data sheet applies to the mc68hc705b5, with the exceptions outlined in this appendix. c.1 features 6206 bytes eprom (including 14 bytes user vectors) no eeprom bootstrap firmware simultaneous programming of up to 4 bytes data protection for program code optional pull-down resistors on port b and port c mc68HC05B6 mask options are programmable using control bits held in the options register 52-pin plcc and 56-pin sdip packages high speed version not available 161 162 163 164 165
freescale c-2 mc68HC05B6 rev. 4.1 mc68hc705b5 14 figure c-1 mc68hc705b5 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit programmable timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator 176 bytes ram cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp6 256 bytes eprom1 6206 bytes 2 / 32 plma d/a plmb d/a 8-bit 496 bytes bootstrap rom eprom (including 14 bytes user vectors) 166 167 168 169 170
mc68HC05B6 rev. 4.1 freescale c-3 mc68hc705b5 14 figure c-2 memory map of the mc68hc705b5 port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $1ff0 stack ram (176 bytes) $0300 $0200 $1f00 $0050 port a data direction register port b data direction register port c data direction register eprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f page 0 user eprom (48 bytes) bootstrap romi (256 bytes) user eprom (5888 bytes) bootstrap romii (240 bytes) $0800 user eprom1 (256 bytes) $1efe options register reserved mc68hc705b5 registers options register $1efe user vectors (14 bytes) $1ff2?3 sci timer overflow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $1ff2?3 $1ff2?3 $1ff2?3 $1ff2?3 $1ff2?3 $1ff2?3 171 172 173 174 175
freescale c-4 mc68HC05B6 rev. 4.1 mc68hc705b5 14 table c-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 undefined port b data (portb) $0001 undefined port c data (portc) $0002 pc2/ eclk undefined port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 undefined port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eprom/eclk control $0007 eppt (1) elat epgm eclk u?00 0uuu a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (2) intp intn inte sfa sfb sm wdog (3) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl uuuu sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 uuuu input capture high 1 $0014 undefined input capture low 1 $0015 undefined output compare high 1 $0016 undefined output compare low 1 $0017 undefined timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c undefined input capture low 2 $001d undefined output compare high 2 $001e undefined output compare low 2 $001f undefined options (optr) (4) $1efe epp 0 rtim rwat wwat pbpd pcpd not affected (1) this bit reflects the state of the epp bit in the options register ($1efe) at reset. (2) this bit is set each time the device is powered-on. (3) the state of the wdog bit after reset depends on the mask op tion selected; ?1? = watchdog enabled and ?0? = watchdog disable d. (4) because this register is implemented in eprom, reset has no effect on the st ate of the individual bits. 176 177 178
mc68HC05B6 rev. 4.1 freescale c-5 mc68hc705b5 14 c.2 eprom the mc68hc705b5 has a total of 6206 bytes of eprom, 256 bytes being reserved for the eprom1 array (see figure c-2 ). the epp bit (eprom protect) is not operative on the eprom1 array, making it possible to program it after the main eprom has been programmed and protected. the reset and interrupt vectors are located at $1ff2-$1fff and the eprom control register described in section c.3.1 is located at address $0007. the eprom array is supplied by the vpp6 pin in both read and programming modes. typically the user?s software will be loaded in a programm ing board where vpp6 is controlled by one of the bootstrap loader routines (bootloader mode). it wil l then be placed in an application where no programming occurs (user mode). in this case the vpp6 pin should be hardwired to v dd . an erased eprom byte reads as $00. warning: a minimum v dd voltage must be applied to the vpp6 pin at all times, including power-on, as a lower voltage could dama ge the device. unless otherwise stated, eprom programming is guaranteed at ambient (25 c) temperature only c.2.1 eprom programming operation the user program can be used to program some eprom locations, provided the proper procedure is followed. in particular, the progra mming sequence must be running in ram, as the eprom will not be available for code execution whil e the elat bit is set. the vpp6 switching must occur externally, after the epgm bit is set, for example, under the control of a signal generated on a pin by the programming routine. note: unless the part has a window for reprogramming, only the cumulative programming of bits to logic 1 is possible if multiple programming is made on the same byte. to allow simultaneous programming of up to 4 bytes, they must be in the same group of addresses which share the same most significant addr ess bits; only the two lsbs can change.
freescale c-6 mc68HC05B6 rev. 4.1 mc68hc705b5 14 c.3 eprom registers c.3.1 eprom con trol register bit 7 ? factory use only this bit is strictly for factory use only and will always read zero. eppt ? eprom protect test bit this bit is a copy of the eprom protect bit (epp ) located in the option register. when elat is set, the eppt bit can be tested by the software to c heck if the eprom array is protected or not, since the eprom content is not available when elat is set. por or external reset modifies th is bit to reflect the state of t he epp bit in the op tions register. elat ? eprom programming latch enable bit 1 (set) ? when set, this bit allows latching of the address and up to 4 data bytes for further programming, provided epgm is zero. 0 (clear) ? when cleared, program and in terrupt routines can be executed and data can be read in the eprom or firmware rom. stop, power-on and external reset clear this bit. epgm ? eprom programming bit this bit is the eprom program enable bit. it can be set to ?1? to enable programming only after elat is set and at least one byte is written to the eprom. it is not possible to clear epgm by software, but clearing elat will always clear epgm. eclk ? external clock option bit see section 4.3 . address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eprom/eclk control $0007 eppt (1) (1) this bit is a copy of the epp bit in the options register at $1efe and therefore its state on reset will be the same as that for the epp bit. elat epgm eclk u?00 0uuu
mc68HC05B6 rev. 4.1 freescale c-7 mc68hc705b5 14 c.4 options register (optr) note: this register can only be written to while the device is in bootloader mode. bit 7 ? factory use only warning: this bit is strictly for factory use only and will always read zero to avoid accidental damage to the device. any attempt to write to this bit could result in physical damage. epp ? eprom protect this bit protects the c ontents of the main eprom against accid ental modification; it has no effect on reading or executing code in the eprom. 1 (set) ? eprom contents are protected. 0 (clear) ? eprom contents are not protected. rtim ? reset time this bit can modify t porl , i.e. the time that the reset pin is kept low following a power-on reset. this feature is handled in the rom part via a mask option. 1 (set) ? t porl = 16 cycles. 0 (clear) ? t porl = 4064 cycles. rwat ? watchdog after reset this bit can modify the status of the watchdog counter after reset. 1 (set) ? the watchdog will be active immediately following power-on or external reset (except in bootstrap mode). 0 (clear) ? the watchdog system will be disabled after power-on or external reset. wwat ? watchdog during wait mode this bit can modify the status of the watchdog counter during wait mode. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset options (optr) (1) (1) this register is implemented in eprom, therefore reset has no effect on the st ate of the individual bits. $1efe epp 0 rtim rwat wwat pbpd pcpd not affected
freescale c-8 mc68HC05B6 rev. 4.1 mc68hc705b5 14 1 (set) ? the watchdog will be active during wait mode. 0 (clear) ? the watchdog system will be disabled during wait mode. pbpd ? port b pull-down resistors 1 (set) ? pull-down resistors are connec ted to all 8 pins of port b; the pull-down, r pd , is active only while the pin is an input. 0 (clear) ? no pull-down resistors are connected. pcpd ? port c pull-down resistors 1 (set) ? pull-down resistors are connec ted to all 8 pins of port c; the pull-down, r pd , is active only while the pin is an input. 0 (clear) ? no pull-down resistors are connected. the combination of bit 0 and bit 1 allows the option of pull-down resistors on 0, 8 or 16 inputs. this feature is not available on the mc68HC05B6. c.5 bootstrap mode the 432 bytes of self-check firmware on t he mc68HC05B6 are replaced with 496 bytes of bootstrap firmware. the bootstrap firmware located from $0200 to $02ff and $1f00 to $1fef can be used to program the eprom, to check if the eprom is erased and to load and execute data in ram. when the mc68hc705b5 is placed in the bootstrap mode, the bootstrap reset vector is fetched and the bootstrap firmware starts to execute. ta bl e c - 2 shows the conditions required to enter each level of bootstrap mode on the rising edge of reset . the hold time on the irq and tcap1 pins after the external reset pin is brought high is two clock cycles. table c-2 mode of operation selection irq pin tcap1 pin pd2 pd3 pd4 mode v ss to v dd v ss to v dd x x x single chip + 9 volts v dd 0 1 0 erased eprom verification + 9 volts v dd x 0 0 eprom parallel bootstrap load + 9 volts v dd x 1 1 eprom (ram) serial bootstrap load and execute + 9 volts v dd x 0 1 ram parallel bootstrap load and execute x = don?t care
mc68HC05B6 rev. 4.1 freescale c-9 mc68hc705b5 14 the bootstrap program first copies part of itself into ram, as the program cannot be executed in rom during verification/programming of the eprom. it then sets the tcmp1 output to a logic high level. figure c-3 modes of operation flow chart (1 of 2) tcap1 set? irq at 9v? eprom erased? pd2 set? pd3 set? pd4 set? reset program eprom; parallel load; green led flashes programming ok? user mode red led on green led on non-user mode red led on green led on non-user mode a y y y y yy n n n n n n y bootstrap mode eprom not erased eprom verified parallel eprom bootstrap bad eprom programming n
freescale c-10 mc68HC05B6 rev. 4.1 mc68hc705b5 14 figure c-4 modes of operation flow chart (2 of 2) programming ok? negative address? pd4 set? pd3 set? transmit last four programmed locations a red led off receive address receive four data execute ram program at $0083 green led on load next ram byte ram full? execute ram program at $0050 program eprom data at address; green led flashes red led on n y y y y y n n n serial eprom (ram) bootstrap bad eprom bootstrap ram programming n
mc68HC05B6 rev. 4.1 freescale c-11 mc68hc705b5 14 c.5.1 erased eprom verification the flowchart in figure c-3 and figure c-4 shows that the on-chip bootstrap routines can be used to check if the eprom is erased (all $00s). if a non $00 byte is detected, the red led stays on and the routine will stay in a loop. only when the whole eprom content is verified as erased will the green led be turned on. c.5.2 eprom parallel bootstrap load when this mode is selected, the eprom is l oaded in increasing address order with non eprom segments being skipped by the loader. simultaneous programming is performed by reading four bytes of data before actual programming is perform ed, thus dividing the load ing time of the internal eprom by four. when pd2=0, the programming time is set to 5 m illiseconds and the program/verify routine takes approximately 15 seconds. parallel data is entered through port a, while the 13-bit address is output on port b and pc0 to pc4. if the data comes from an external eprom, the handshake can be disabled by connecting together pc5 and pc6. if the data is supplied via a parallel interface, handshaking will be provided by pc5 and pc6 according to the timing diagram of figure c-5 . during programming, the green led flashes at about 3 hz. upon completion of the programming operation, the eprom content is checked against the external data source. if programming is verified the green led stays on, while an error causes the red led to be turned on. figure c-6 shows a circuit that can be used to program the eprom (or to load and execute data in the ram). note: the entire eprom can be loaded from the extern al source; if it is desired to leave a segment undisturbed, the data for th is segment should be all zeros. figure c-5 timing diagram with handshake data read data read address hdsk out (pc5) data hdsk in (pc6) f29
freescale c-12 mc68HC05B6 rev. 4.1 mc68hc705b5 14 figure c-6 eprom(ram) parallel boot strap schematic diagram pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 vdd osc1 osc2 tcap1 irq reset vss a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 gnd oe vcc pgm vpp 14 22 10 9 8 7 6 5 4 1262728 12 13 15 16 17 18 19 11 3 +5v 1 2 p1 gnd +5v 100 f 22pf 4.0 mhz 1n914 1k ? 1.0 f 22pf 10m ? 100k ? 1n914 reset run 0.01 f tdo sclk rdi vrl tcap2 pd7 pd6 pd5 pd3 pd2 pd1 pd0 pd4 +5v 3 v pp vpp6 pc7 pc5 pc4 pc3 pc2 pc1 pc0 pc6 nc 24 21 23 2 a9 a8 a10 a12 ce a11 a12 a11 a10 a9 a8 hdsk out hdsk in short circuit if handshake not used 100 k ? nc tcmp1 tcmp2 plma plmb 470 ? 470 ? red led green led 4k7 ? 4k7 ? 12 k ? bc239c bc309c 10 k ? 27c64 + + vrh red led ? programming failed green led ? programming ok 25 1nf 1n5819 1 k ? + ram eprom 47 f + 20 mc68hc705b5 note: this circuit is recommended for programming only at 25 c and not for use in the end application, or at temperatures other than 25 c. if used in the end application, vpp6 should be tied to vdd to avoid damaging the device.
mc68HC05B6 rev. 4.1 freescale c-13 mc68hc705b5 14 c.5.3 eprom (ram) serial b ootstrap load and execute the serial routine communicates through the sci with an external host, typically a pc, by means of an rs232 link at 9600 baud, 8-bit, no parity and full duplex. data format is not ascii, but 8-bit binary, so a complementary program must be run by the host to supply the required format. such a program is available for the ibm pc from freescale. the eprom bootstrap routines are used to cu stomise the otp eprom. to increase the speed of programming, four bytes are programmed in parallel while the data is simultaneously transmitted and received in full duplex. this implies that while 4 bytes are being programmed, the next 4 bytes are received and the preceding 4 bytes are echoed. the format accepted by the serial loader is as follows: [address n high] [address n low] [data(n)] [data (n+1)] [data (n+2)] [data (n+3)] address n must have the two lsbs at zero so that n, n+1, n+2 and n+3 have identical msbs. these blocks of four bytes do not need to be co ntiguous, as a new address is transmitted for each new group. the protocol is as follows: 1 the mc68hc705b5 sends the last two bytes programmed to the host as a prompt; this allows verification by the host of proper programming. 1) in response to the first byte prompt, the host sends the first address byte. 2) after receiving the first address byte, the mc68hc705b5 sends the next byte programmed. 3) the exchange of data continues until the mc68hc705b5 has sent the four data bytes and the host has sent th e 2 address data bytes and 4 data bytes. 4) if the data is non zero, it is programmed at the address provided, while the next address and bytes are received and the previous data is echoed. 5) loop to 1. after reset, the mc68hc705b5 serial bootstrap routine will first echo two blocks of four bytes at $0000, as no data is programmed yet. if the data sent in is $00, no programming in the eprom takes place, and the contents of the accessed location are returned as a prompt. the entire eprom memory can be read in this fashion (serial dump). the red led will be on if the data read from the eprom is not $00. serial ram loading and execute can be accomplished in this mode. a ram byte will be written if the address sent by the host in the serial protocol points to the ram. in the ram bootloader mode, all interrupt ve ctors are mapped to pseudo-vectors in ram (see ta bl e c - 3 ). this allows programmers to use t heir own service-routine addresses. each pseudo-vector is allowed three bytes of spac e rather than the two bytes for normal vectors, because an explicit jump (jmp) opcode is nee ded to cause the desired jump to the user?s service-routine address.
freescale c-14 mc68HC05B6 rev. 4.1 mc68hc705b5 14 a 10-byte stack is also reserved at the top of th e ram allowing, for example, one interrupt and two sub-routine levels. program execution is triggered by sending a negativ e (bit 7 set) high address; execution starts at address xadr ($0083). the ram addresses between $0050 and $0082 are used by the loader and are therefore not available to the user during serial loading/executing. refer to figure c-7 shows a suitable circuit. figure c-9 shows address and data bus timing. c.5.4 ram parallel bootstrap load and execute the ram bootstrap program will start loading the ram with external data (e.g. from a 2564 or 2764 eprom). before loading a new byte, the state of the pd4/an4 pin is checked; if this pin goes to level ?0?, or if the ram is full, then contro l is given to the loaded program at address $0050. if the data is supplied by a parallel interface, handshaking will be provided by pc5 and pc6 according to figure c-10 . if the data comes from an external eprom, the handshake can be disabled by connecting together pc5 and pc6. figure c-8 shows a circuit that can be used to load the ram with short test programs. up to 8 programs can be loaded in turn from the eprom. selection is accomplished by means of the switches connected to the eprom higher address lines (a8 through a10). if the user program sets pc0 to level ?1?, the external eprom will be disabled, rendering both port a outputs and port b inputs available. the eprom parallel bootstrap loader circuit ( figure c-6 ) can also be used, provided vpp is tied to v dd . the high order address lines will be at zero. the leds will stay off. table c-3 bootstrap vector targets in ram vector targets in ram sci interrupt $00e4 timer overflow $00e7 timer output compare $00ea timer input capture $00ed irq $00f0 swi $00f3
mc68HC05B6 rev. 4.1 freescale c-15 mc68hc705b5 14 figure c-7 eprom (ram) serial bootstrap schematic diagram red ? programming error green ? programming ok 40 vpp6 pc7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 vdd osc1 osc2 tcap1 irq reset vss 1 2 p1 gnd +5v 1n914 1k ? 1.0 f 100k ? 1n914 reset run 0.01 f 3 v pp pc5 pc4 pc3 pc2 pc1 pc0 pc6 plma plmb 470 ? 470 ? red led green led + + vrh 22 f 22 f 22 f 2 x 3k ? 1 2 3 4 8 6 7 5 11 12 13 14 15 16 5 3 2 1 22 f rs232 connector max 232 +5v 9600 bd 8-bit no parity 19 18 20 21 50 52 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 14 13 12 5 43 44 45 46 47 48 49 23 2 1 51 22 8 10 41 7 vrl tcap2 tcmp1 tcmp2 sclk nc 10nf 47 f pd0 pd4 pd1 pd2 pd5 pd6 pd7 + + + + 22pf 4.0 mhz 22pf 10m ? 4k7 ? 4k7 ? 12 k ? bc239c bc309c 10 k ? 1nf 1n5819 1 k ? + serial boot erase check 47 f + pd3 4 rdi tdo erase check red ? eprom not erased green ? eprom erased serial boot mc68hc705b5 3 note: a minimum v dd voltage must be applied to the vpp6 pin at all times, including power-on, as a lower voltage could damage the device. unless otherwise stated, eprom programming is guaranteed at ambient (25 c) temperature only
freescale c-16 mc68HC05B6 rev. 4.1 mc68hc705b5 14 figure c-8 ram parallel bootstrap schematic diagram pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb6 pb7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 vdd tcap2 tcmp2 tcmp1 plmb plma sclk tdo rdi vrh vrl pd7 pd6 pd5 pd3 pd2 pd1 pd0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 nc osc1 osc2 tcap1 irq reset pd4 vpp6 vss a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 gnd oe a8 a9 a10 a11 a12 ce vcc pgm vpp 20 2 25 24 23 14 22 10 9 8 7 6 5 4 1262728 21 12 13 15 16 17 18 19 11 3 +5v 3 x 4.7k ? +5v +5v 16 x 100k ? 1 2 p1 gnd +5v 100 f 22pf 4.0 mhz 1n914 1k ? 1.0 f 22pf 10m ? 100k ? 1n914 reset run 0.01 f u1 2764 +5v 18 x 100 k ? + + nc mc68hc705b5
mc68HC05B6 rev. 4.1 freescale c-17 mc68hc705b5 14 c.5.5 bootstrap loader timing diagrams figure c-9 eprom parallel bootstrap loader timing diagram t cooe t ade t dhe address data t ade t dhe t ade t dhe t ade t dhe t cooe t cooe t cdde t ade max (address to data delay) 5 machine cycles t dha min (data hold time) 14 machine cycles t cooe (load cycle time) 117 machine cycles < t cooe < 150 machine cycles t cdde (programming cycle time) t cooe + t prog (5ms nominal) 1 machine cycle = 1/(2f 0 (xtal))
freescale c-18 mc68HC05B6 rev. 4.1 mc68hc705b5 14 figure c-10 ram parallel loader timing diagram t adr t dhr address data t cr pd4 t exr max t ho t hi max pc5 out pc6 in t adr max (address to data delay; pc6=pc5) 16 machine cycles t dhr min (data hold time) 4 machine cycles t cr (load cycle time; pc6=pc5) 49 machine cycles t ho (pc5 handshake out delay) 5 machine cycles t hi max (pc6 handshake in, data hold time) 10 machine cycles t exr max (max delay for transition to be recognised during this cycle; pc6=pc5 30 machine cycles 1 machine cycle = 1/(2f 0 (xtal))
mc68HC05B6 rev. 4.1 freescale c-19 mc68hc705b5 14 c.6 dc electrical characteristics note: the complete table of dc electrical characteristics can be found in section 11.2. the values contained in the following table should be used in conjunction with those quoted in that section. c.7 control timing note: the complete table of control timing can be found in section 11.4. the values contained in the following table should be used in conjunction with those quoted in that section. table c-4 additional dc electrical characteristics for mc68hc705b5 (v dd = 5 vdc 10%, v ss = 0 vdc, t a = 25 c) characteristic symbol min typ max unit input current port b and port c pull-down (v in =v ih ) i rpd 80 a eprom absolute maximum voltage v pp6 max v dd ?18v eprom programming voltage v pp6 15.0 15.5 16 v eprom programming current i pp6 ??18ma eprom read voltage v pp6r v dd v dd v dd v table c-5 additional control timing for mc68hc705b5 (v dd = 5 vdc 10%, v ss = 0 vdc, t a = 25 c) characteristic symbol min typ max unit eprom programming time t prog 5?20ms
freescale c-20 mc68HC05B6 rev. 4.1 mc68hc705b5 14 this page left bl ank intentionally
mc68HC05B6 rev. 4.1 freescale d-1 mc68hc05b16 14 d mc68hc05b16 the mc68hc05b16 is a device similar to the mc68HC05B6, but with increased ram, rom and self-check rom sizes. the entire mc68HC05B6 data sheet, including the electrical characteristics, applies to the mc68hc05b16, wit h the exceptions outlined in this appendix. d.1 features 15 kbytes user rom 352 bytes of ram 496 bytes self-check rom 52-pin plcc, 56-pin sdip and 64-pin qfp packages high speed version available maskset errata this errata section outlines the differences between previously available masksets (d20j, f62j and g28f) an d all other masksets. unless otherwise stated, the main body of appendix d refers to all these other masksets with any differences being noted in this errata section. certain mc68hc05b16 masksets contain t he same oscillator circuitry as the mc68HC05B6 (see section 2.5.8.3 ). these are denoted by d20j, f62j and g28f. 179 180 181 182 183
freescale d-2 mc68HC05B6 rev. 4.1 mc68hc05b16 14 d.2 self-check routines the self-check routines for the mc68hc05b16 are identical to those of the mc68hc05b4 with the following exception. the count byte on the mc68hc05b16 can be any value up to 256 ($00). the first 176 bytes are loaded into ram i and the remainder is loaded into ram ii starting at $0250. table d-1 mode of operation selection irq pin tcap1 pin pd3 pd4 mode v ss to v dd v ss to v dd x x single chip 2v dd v dd 0xself check 2v dd v dd 1 0 serial ram loader 2v dd v dd 1 1 jump to any address 184
mc68HC05B6 rev. 4.1 freescale d-3 mc68hc05b16 14 figure d-1 mc68hc05b16 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp1 256 bytes eeprom charge pump 2 / 32 plma d/a plmb d/a 8-bit 15120 bytes rom 352 bytes static ram 496 bytes self-check rom
freescale d-4 mc68HC05B6 rev. 4.1 mc68hc05b16 14 d.3 external clock when using an external clock the osc1 and osc2 pins should be driven in antiphase, as shown in figure d-2 . the t oxov or t ilch specifications (see section 11.4 ) do not apply when using an external clock input. the equivalent specification of the external clock source should be used in lieu of t oxov or t ilch . figure d-2 oscillator connections ceramic resonator 2 ? 4mhz unit r s (typ) 10 ? c 0 40 pf c 1 4.3 pf c osc1 30 pf c osc2 30 pf r p 1 ? 10 m ? q 1250 ? crystal 2mhz 4mhz unit r s (max) 400 75 ? c 0 57pf c 1 812 ? f c osc1 15 ? 40 15 ? 30 pf c osc2 15 ? 30 15 ? 25 pf r p 10 10 m ? q 30 000 40 000 ? osc1 osc2 mcu c osc2 c osc1 osc1 osc2 mcu nc external clock osc1 osc2 r s c 1 l c 0 (d) typical crystal and ce ramic resonator parameters (c) external clock source connections (b) crystal equivalent circuit (a) crystal/ceramic resonator oscillator connections
mc68HC05B6 rev. 4.1 freescale d-5 mc68hc05b16 14 figure d-3 memory map of the mc68hc05b16 port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $3ff0 stack ram1 (176 bytes) $0250 $0200 $3e00 $0050 port a data direction register port b data direction register port c data direction register eeprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f page 0 user rom (48 bytes) user rom (15104 bytes) self-check rom (496 bytes) $0300 options register unprotected (31 bytes) protected (224 bytes) eeprom (256 bytes) $0101 $0120 $0100 options register reserved mc68hc05b16 registers ram11 (176 bytes) $3dfe user vectors (14 bytes) $3ff2?3 sci timer overflow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $3ff4?5 $3ff6?7 $3ff8?9 $3ffa?b $3ffc?d $3ffe?f
freescale d-6 mc68HC05B6 rev. 4.1 mc68hc05b16 14 table d-2 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 undefined port b data (portb) $0001 undefined port c data (portc) $0002 pc2/ eclk undefined port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 undefined port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eeprom/eclk control $0007 0 0 0 0 eclk e1era e1lat e1pgm 0000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl undefined sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 undefined input capture high 1 $0014 undefined input capture low 1 $0015 undefined output compare high 1 $0016 undefined output compare low 1 $0017 undefined timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c undefined input capture low 2 $001d undefined output compare high 2 $001e undefined output compare low 2 $001f undefined options (optr) (3) $0100 ee1p sec not affected (1) this bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent upon t he mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) this register is implemented in eeprom; theref ore reset has no effect on the individual bits.
mc68HC05B6 rev. 4.1 freescale e-1 mc68hc705b16 14 e mc68hc705b16 the mc68hc705b16 is a device similar to the mc68HC05B6, but with increased ram and 15 kbytes of eprom instead of 6 kbytes of rom. in addition, the self-check routines available in the mc68HC05B6 are replaced by bootstrap firmware. the mc68hc705b16 is an otprom (one-time programmable rom) version of the mc 68hc05b16, meaning that once the application program has been loaded in the eprom it ca n never be erased. the entire mc68HC05B6 data sheet applies to the mc68hc705b16, with t he exceptions outlined in this appendix. to ensure correct operation of the mc68hc7 05b16 after power-on, the device must be reset a second time after power-on. this can be done in software using the mc68hc705b16 watchdog. the following software sub-routine should be used: reset2 bset 0, $0c start watchdog stop stop causes immediate watchdog system reset the interrupt vector at $3ff0 and $3f f1 must be initialised with the reset2 address value. 185 186 187 188 189
freescale e-2 mc68HC05B6 rev. 4.1 mc68hc705b16 14 e.1 features 15 kbytes eprom 352 bytes of ram 576 bytes bootstrap rom simultaneous programming of up to 8 bytes of eprom optional pull-down resistors available on all port b and port c pins 52-pin plcc and 64-pin qfp packages high speed version not available note: the electrical characteristics of the mc68HC05B6 as provided in section 11 do not apply to the mc68hc705b16. data specif ic to the mc68hc705b16 can be found in this appendix. figure e-1 mc68hc705b16 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp1 256 bytes eeprom charge pump 2 / 32 plma d/a plmb d/a 8-bit 15168 bytes eprom 352 bytes static ram 576 bytes vpp6 bootstrap rom 190 191 192 193 194
mc68HC05B6 rev. 4.1 freescale e-3 mc68hc705b16 14 figure e-2 memory map of the mc68hc705b16 port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $3ff0?1 stack ram1 (176 bytes) $0250 $0200 $3e00 $0050 port a data direction register port b data direction register port c data direction register e/eeprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f page 0 user eprom (48 bytes) user eprom (15104 bytes) bootstrap rom11 (496 bytes) $0300 options register unprotected (31 bytes) protected (224 bytes) eeprom (256 bytes) $0101 $0120 $0100 options register reserved mc68hc705b16 registers ram11 (176 bytes) $3dfe $3dff mask option register mask option register $3dfe bootstrap rom1 (80 bytes) user vectors (14 bytes) $3ff2?3 sci timer overflow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $3ff4?5 $3ff6?7 $3ff8?9 $3ffa?b $3ffc?d $3ffe?f 195 196 197 198 199
freescale e-4 mc68HC05B6 rev. 4.1 mc68hc705b16 14 table e-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 undefined port b data (portb) $0001 undefined port c data (portc) $0002 pc2/ eclk undefined port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 undefined port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eprom/eeprom/eclk control $0007 e6lat e6pgm eclk e1era e1lat e1pgm 0000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl undefined sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 undefined input capture high 1 $0014 undefined input capture low 1 $0015 undefined output compare high 1 $0016 undefined output compare low 1 $0017 undefined timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c undefined input capture low 2 $001d undefined output compare high 2 $001e undefined output compare low 2 $001f undefined options (optr) (3) $0100 ee1p sec not affected mask option register (mor) (4) $3dfe rtim rwat wwat pbpd pcpd not affected (1) this bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent upon t he mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) this register is implemented in eeprom; theref ore reset has no effect on the individual bits. (4) this register is implemented in eprom; theref ore reset has no effect on the individual bits. 200 201 202 203 204
mc68HC05B6 rev. 4.1 freescale e-5 mc68hc705b16 14 e.2 external clock when using an external clock the osc1 and os c2 pins should be driven in antiphase (see figure d-2 ). the t oxov or t ilch specifications (see section e.8 ) do not apply when using an external clock input. the equivalent specification of the external clock source should be used in lieu of t oxov or t ilch . e.3 eprom the mc68hc705b16 memory map is given in figure e-2 . the device has a total of 15168 bytes of eprom (including 14 bytes for user vectors) and 256 bytes of eeprom. the eprom array is supplied by the vpp6 pin in both read and program modes. typically the user?s software would be loaded into a programming board where v pp6 is controlled by one of the bootstrap loader routines. it would then be placed in an application where no programming occurs. in this case the vpp6 pi n should be hardwired to v dd . warning: a minimum v dd voltage must be applied to the vpp6 pin at all times, including power-on. failure to do so could result in permanent damage to the device. unless otherwise stated, eprom programmi ng is guaranteed at ambient (25 c) temperature only. e.3.1 eprom read operation the execution of a program in the eprom addres s range or a load from the eprom are both read operations. the e6lat bit in the eprom/eepr om control register should be cleared to ?0? which automatically resets the e6pgm bit. in this way the eprom is read like a normal rom. reading the eprom with the e6lat bit set will gi ve data that does not correspond to the actual memory content. as interrupt vectors are in eprom, they will not be loaded when e6lat is set. similarly, the bootstrap rom routines cannot be executed when e6lat is set. in read mode, the vpp6 pin must be at the v dd level. when entering the stop mode, the eprom is automatically set to the read mode. note: an erased byte reads as $00. e.3.2 eprom program operation typically the eprom will be programmed by the bo otstrap routines resident in the on-chip rom. however, the user program can be used to program some eprom locations if the proper procedure is followed. in particular, the progra mming sequence must be running in ram, as the 205 206 207 208 209
freescale e-6 mc68HC05B6 rev. 4.1 mc68hc705b16 14 eprom will not be available for code execution while the e6lat bit is set. the v pp6 switching must occur externally after the e6pgm bit is se t, for example under control of a signal generated on a pin by the programming routine. note: when the part becomes a prom, only the cumulative programming of bits to logic ?1? is possible if multiple programming is made on the same byte. to allow simultaneous programming of up to eight bytes, these bytes must be in the same group of addresses which share the same most signific ant address bits; only t he three least significant bits can change. e.3.3 eprom/eeprom/eclk control register e6lat ? eprom programming latch enable bit 1 (set) ? address and up to eight data bytes can be latched into the eprom for further programming providing the e6pgm bit is cleared. 0 (clear) ? data can be read from the epr om or firmware rom; the e6pgm bit is reset to zero when e6lat is ?0?. stop, power-on and external reset clear the e6lat bit. note: after the t era1 erase time or t prog1 programming time, the e6lat bit has to be reset to zero in order to clear the e6pgm bit. e6pgm ? eprom program enable bit this bit is the eprom program enable bit. it can be set to ?1? to enable programming only after e6lat is set and at least one byte is written to the eprom. it is not possible to clear this bit using software but clearing e6 lat will always clear e6pgm. note: the e6pgm bit can never be set while the e6lat bit is at zero. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eprom/eeprom/eclk control $0007 e6lat e6pgm eclk e1era e1lat e1pgm 0000 0000 table e-2 eprom control bits description e6lat e6pgm description 0 0 read/execute in eprom 1 0 ready to write address/data to eprom 1 1 programming in progress 210 211 212
mc68HC05B6 rev. 4.1 freescale e-7 mc68hc705b16 14 eclk see section 4.3 . e1era ? eeprom erase/programming bit providing the e1lat and e1pgm bits are at logic one, this bit indicates whether the access to the eeprom is for erasing or programming purposes. 1 (set) ? an erase operation will take place. 0 (clear) ? a programming operation will take place. once the program/erase eeprom address has been selected, e1era cannot be changed. e1lat ? eeprom programming latch enable bit 1 (set) ? address and data can be latched into the eeprom for further program or erase operations, providing the e1pgm bit is cleared. 0 (clear) ? data can be read from t he eeprom. the e1era bit and the e1pgm bit are reset to zero when e1lat is ?0?. stop, power-on and external reset clear the e1lat bit. note: after the t era1 erase time or t prog1 programming time, the e1lat bit has to be reset to zero in order to clear the e1era bit and the e1pgm bit. e1pgm ? eeprom charge pump enable/disable 1 (set) ? internal charge pump generator switched on. 0 (clear) ? internal charge pump generator switched off. when the charge pump generator is on, the resulti ng high voltage is applied to the eeprom array. this bit cannot be set before the data is select ed, and once this bit has been set it can only be cleared by clearing the e1lat bit. a summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in ta b l e e - 3 . note: the e1pgm and e1era bits are cleared when the e1lat bit is at zero. table e-3 eeprom control bits description e1era e1lat e1pgm description 0 0 0 read condition 0 1 0 ready to load address/data for program/erase 0 1 1 byte programming in progress 1 1 0 ready for byte erase (load address) 1 1 1 byte erase in progress
freescale e-8 mc68HC05B6 rev. 4.1 mc68hc705b16 14 e.3.4 mask option register rtim ? reset time this bit can modify the time t porl , where the reset pin is kept low after a power-on reset. 1 (set) ? t porl = 16 cycles. 0 (clear) ? t porl = 4064 cycles. rwat ? watchdog after reset this bit can modify the status of the watchdog counter after reset. usually, the watchdog system is disabled after power-on or external reset but when this bit is set, it will be active immediately after the following resets (except in bootstrap mode). wwat ? watchdog during wait mode this bit can modify the status of the watchdog counter in wait mode. normally, the watchdog system is disabled in wait mode but when this bit is set, the watchdog will be active in wait mode. pbpd ? port b pull-down this bit, when programmed, connects a resistive pull-down on each pin of port b. this pull-down, r pd , is active on a given pin only while it is an input. pcpd ? port c pull-down this bit, when programmed, connects a resistive pul l-down on each pin of port c. this pull-down, r pd , is active on a given pin only while it is an input. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset mask option register (mor) (1) (1) this register is implemented in eprom; ther efore reset has no effect on the individual bits. $3dfe rtim rwat wwat pbpd pcpd not affected
mc68HC05B6 rev. 4.1 freescale e-9 mc68hc705b16 14 e.3.5 eeprom options register (optr) ee1p ? eeprom protect bit in order to achieve a higher degr ee of protection, the eeprom is effectively split into two parts, both working from the vpp1 charge pump. part 1 of the eeprom array (32 bytes from $0100 to $011f) cannot be protected; part 2 (224 bytes from $0120 to $01ff) is protected by the ee1p bit in the options register. 1 (set) ? part 2 of the eeprom array is not protected; all 256 bytes of eeprom can be accessed for any read, erase or programming operations. 0 (clear) ? part 2 of the eeprom array is protected; any attempt to erase or program a location will be unsuccessful. when this bit is set to 1 (erased), the protection will remain until the next power-on or external reset. ee1p can only be written to ?0? when the e1lat bit in the eeprom c ontrol register is set. note: the eeprom1 protect function is disabled while in bootstrap mode. sec ? secure bit this bit allows the eprom and eeprom1 to be secu red from external access. when this bit is in the erased state (set), the eprom and eepr om1 content is not secured and the device may be used in non user mode. when the sec bit is programmed to ?zero?, the eprom and eeprom1 content is secured by prohibiting entry to the non user mode. to deactivate the secure bit, the eprom has to be erased by exposure to a high density ultraviolet light, and the device has to be entered into the eprom erase verification mode with pd1 set. when the sec bit is changed, its new value will have no effect until the next power-on or external reset. 1 (set) ? eeprom/eprom not protected. 0 (clear) ? eeprom/eprom protected. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset options (optr) (1) (1) this register is implemented in eeprom; theref ore reset has no effect on the individual bits. $0100 ee1p sec not affected
freescale e-10 mc68HC05B6 rev. 4.1 mc68hc705b16 14 e.4 bootstrap mode the 432 bytes of self-check firmware on the mc68HC05B6 are replaced by 576 bytes of bootstrap firmware. a detailed description of the modes of operation within bootstrap mode is given below. the bootstrap program in mask rom address locations $0200 to $024f and $3e00 to $3fef can be used to program the eprom and the eeprom, to check if the eprom is erased or to load and execute data in ram. after reset, while going to the bootstrap mode, the vector located at address $3fee and $3fef (reset) is fetched to start execution of the bo otstrap program. to place the part in bootstrap mode, the irq pin should be at + 9v with the tcap1 pin ?high? dur ing transition of the reset pin from low to high. the hold time on the irq and tcap1 pins is two clock cycles after the external reset pin is brought high. when the mc68hc705b16 is placed in the bootstrap mode, the bootstrap reset vector is fetched and the bootstrap firmware starts to execute. ta b l e e - 4 shows the conditions required to enter each level of bootstrap mode on the rising edge of reset . the bootstrap program first copies part of itse lf in ram (except ?ram parallel load?), as the program cannot be executed in rom during verification/programming of the eprom. it then sets the tcmp1 output to a logic high level. table e-4 mode of operation selection irq pin tcap1 pin pd1 pd2 pd3 pd4 mode v ss to v dd v ss to v dd x x x x single chip + 9 volts v dd 0 0 x 0 erased eprom verification (eev) + 9 volts v dd 1000 erased eprom verification; erase eeprom; eprom/eeprom parallel program/verify + 9 volts v dd 1010 erased eprom verification; erase eeprom; eprom/eeprom/ ram serial bootstrap load and execute + 9 volts v dd x x 0 1 ram parallel bootstrap load and execute (if sec bit = 1) + 9 volts v dd x x 1 1 serial eprom/eeprom/ram bootloader (if sec = 1) x = don?t care
mc68HC05B6 rev. 4.1 freescale e-11 mc68hc705b16 14 figure e-3 modes of operation flow chart (1 of 2) pd3 set? eeprom1 erased? tcap1 set? irq at 9v? pd2 set? pd4 set? reset program eprom; parallel load; green led flashes user mode green led on red led on non-user mode red led on green led on non-user mode a n y y y yn yn n n y n y bootstrap mode eprom not erased eprom verified parallel e/eeprom bootstrap bad eprom programming n pd1 set? bulk erase eeprom1 red led on red led off n y y n b n y erased eprom verification sec bit active? eprom erased? programming ok?
freescale e-12 mc68HC05B6 rev. 4.1 mc68hc705b16 14 figure e-4 modes of operation flow chart (2 of 2) negative address? pd4 set? pd3 set? transmit last four programmed locations a receive address receive four data execute ram program at $008b green led on load next ram byte ram1 full? execute ram program at $0050 program e/eeprom data at address; green led flashes n y y y y n n serial e/eeprom (ram) bootstrap parallel bootstrap ram sec bit set? red led flashes b n y n
mc68HC05B6 rev. 4.1 freescale e-13 mc68hc705b16 14 e.4.1 erased eprom verification if a non $00 byte is detected, the red le d is turned on and the routine stops (see figure e-3 and figure e-4 ). only when the entire eprom content is verified as erased does the green led switch on. pd1 is then checked. if pd1=0, the bootst rap program stops here and no programming occurs until such time as a high level is sensed on pd 1. if pd1=1, the bootstrap program proceeds to erase the eeprom1 for a nominal 100 ms (4.0 mh z crystal). it is then checked for complete erasure; if a non $ff byte is det ected, the red led is turned on, and erase is performed a second time, and so on until total erasure is veri fied. at this point, both eprom and eeprom1 are completely erased and the security bit is cleared. the programming operation can then be performed. a schematic diagram of the circuit re quired for erased eprom verification is shown in figure e-7 . e.4.2 eprom/eeprom parallel bootstrap before the parallel bootstrap routines begin, the erased eprom verification program is executed as described in section e.4.1 . when pd2=0, the programming time is set to 5 milliseconds with the bootstrap program and verify for the eprom taking approximately 15 seconds. the eprom is loaded in increasing address order with non eprom segments being skipped by the loader. simultaneous programming is performed by r eading eight bytes of data before actual programming is performed, thus the loading time of the internal eprom is divided by eight. parallel data is entered through port a, while the 14-bit address is output on port b, pc0 to pc4 and tcmp2. if the data comes from an exte rnal eprom, the handshake can be disabled by connecting together pc5 and pc6. if the data is supplied by a parallel interface, handshaking will be provided by pc5 and pc6 according to the timing diagram of figure e-5 (see also figure e-6 ). during programming, the green led will flash at about 3 hz. upon completion of the programming operation, the contents of the eprom and eeprom1 are checked against the external data source. if programming is verified the green led stays on, while an error will cause the red led to be turned on. figure e-7 is a schematic diagram of a circuit that can be used to program the eprom or to load and execute data in the ram. note: the entire eprom and eeprom1 can be load ed from the external source; if it is desired to leave a segment undisturbed, the data for this segment should be all zeros for eprom data and all $ffs for eeprom1 data.
freescale e-14 mc68HC05B6 rev. 4.1 mc68hc705b16 14 figure e-5 timing diagram with handshake figure e-6 parallel eprom loader timing diagram data read data read address hdsk out (pc5) data hdsk in (pc6) f29 t cooe t ade t dhe address data t ade t dhe t ade t dhe t ade t dhe t cooe t cooe t cdde t ade max (address to data delay) 5 machine cycles t dha min (data hold time) 14 machine cycles t cooe (load cycle time) 117 machine cycles < t cooe < 150 machine cycles t cdde (programming cycle time) t cooe + t prog (5ms nominal for eprom; 10ms for eeprom1)) 1 machine cycle = 1/(2f 0 (xtal))
mc68HC05B6 rev. 4.1 freescale e-15 mc68hc705b16 14 figure e-7 eprom parallel bootstrap schematic diagram vcc 28 1 vpp pgm 27 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 vdd osc1 osc2 tcap1 irq reset vss a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 gnd oe 14 22 10 9 8 7 6 5 4 26 12 13 15 16 17 18 19 11 3 +5v 1 2 p1 gnd +5v 100 f 22pf 4.0 mhz 1n914 1k ? 1.0 f 22pf 100k ? 1n914 reset run 0.01 f tdo sclk rdi vrl tcap2 pd7 pd6 pd5 pd3 pd2 pd1 pd0 pd4 +5v 3 v pp vpp6 pc7 pc5 pc4 pc3 pc2 pc1 pc0 pc6 24 21 23 2 a9 a8 a10 a12 ce a11 a12 a11 a10 a9 a8 hdsk out hdsk in short circuit if handshake not used 100 k ? nc tcmp1 tcmp2 plma plmb 470 ? 470 ? red led green led 4k7 ? 4k7 ? 12 k ? bc239c bc309c 10k ? 27c128 + + vrh red led ? programming failed green led ? programming ok 25 1nf 1n5819 1 k ? + ram eprom green led ? eprom erased 47 f + erase check & boot eprom erase check vpp1 red led ? eprom not erased boot erase check a13 20 mc68hc705b16 mcu note: this circuit is recommended for programming only at 25 c and not for use in the end application, or at temperatures other than 25 c. if used in the end application, vpp6 should be tied to vdd to avoid damaging the device.
freescale e-16 mc68HC05B6 rev. 4.1 mc68hc705b16 14 e.4.3 eeprom/eprom/r am serial bootstrap for erased eprom verification, pd4 must be at ?0?. in this case, er ased eprom verification executes as described in section e.4.1 before control is given to the serial routine. if pd4 is at ?1?, the program initially checks the st ate of the security bit. if the security bit is active (?0?), the program will not enter serial bootstrap and the red led will flash. otherwise the serial bootstrap program will be executed according to figure e-3 and figure e-4 . the serial routine communicates through the sci with an external host, typically a pc, by means of an rs232 link at 9600 ba ud, 8-bit, no parity and full duplex. refer to figure e-8 for a schematic diagram of a suitable circuit. note: data format is not ascii, but 8-bit binary, so a complementary program must be run by the host to supply the required format. such a program is available for the ibm pc from freescale. the eprom bootstrap routines are used to cust omise the otp eprom. to increase the speed of programming the 15 kbytes, four bytes are programmed while the data is simultaneously transmitted back and forward in full duplex. this implies that while 4 bytes are being programmed the next 4 bytes are received and the preceding 4 bytes are echoed. the format accepted by the serial loader is as follows: 1) eprom locations [address n high] [address n low] [data(n)] [data (n+1)] [data (n+2)] [data (n+3)] address n must have the two least significant bits at zero so that n, n+1, n+2 and n+3 have identical most significant bits. these blocks of four bytes do not need to be contiguous, as a new address is transmitted for each new group. 2) eeprom1 locations [address n high] [address n low] [data(n)] [dummy data 1] [d ummy data 2] [dummy data 3] the same four byte protocol of data exchange is used, but only the first data value is programmed at address n. the three following dummy data values must be sent to be in agreement with the protocol, but are not significant. the protocol is as follows: 1) the mc68hc705b16 sends the last two bytes programmed to the host as a prompt; this also allows the host to verify that programming has been carried out correctly. 2) in response to the first byte prompt, the host sends the first address byte. 3) after receiving the first address byte, the mc68hc705b16 sends the next byte programmed.
mc68HC05B6 rev. 4.1 freescale e-17 mc68hc705b16 14 figure e-8 ram/eprom/eeprom serial bootstrap schematic diagram green led ? programming ended flashing green led ? programming 40 vpp6 pc7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 vdd osc1 osc2 tcap1 irq reset vss 1 2 p1 gnd +5v 1n914 1k ? 1.0 f 100k ? 1n914 reset run 0.01 f 3 v pp pc5 pc4 pc3 pc2 pc1 pc0 pc6 plma plmb 470 ? 470 ? red led green led + + vrh 22 f 22 f 22 f 2 x 3k ? 1 2 3 4 8 6 7 5 11 12 13 14 15 16 5 3 2 1 22 f rs232 connector max 232 +5v 9600 bd 8-bit no parity 19 18 20 21 50 52 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 14 13 12 5 4 43 44 45 46 47 48 49 23 2 1 51 22 8 10 41 7 vrl tcap2 tcmp1 tcmp2 sclk nc 10nf 47 f pd0 pd4 pd1 pd2 pd5 pd6 pd7 + + + + 22pf 4.0 mhz 22pf 4k7 ? 4k7 ? 12 k ? bc239c bc309c 10k ? 1nf 1n5819 1 k ? + serial boot erase check 47 f + pd3 rdi tdo erase check red led ? eprom not erased green led ? eprom erased serial boot & serial boot erase check and serial boot eprom erase check vpp1 3 u2 mc68hc705b16 mcu (socket) note: a minimum v dd voltage must be applied to the vpp6 pin at all times, including power-on, as a lower voltage could damage the device. unless otherwise stated, eprom programming is guaranteed at ambient (25 c) temperature only
freescale e-18 mc68HC05B6 rev. 4.1 mc68hc705b16 14 4) the exchange of data continues until the mc68hc705b16 has sent the four data bytes and the host has sent the 2 address data bytes and 4 data bytes. 5) if the data is different from $00 for eprom or $ff for eeprom, it is programmed at the address provided, while the next address and bytes are received and the previous data is echoed. 6) loop to 1. after reset, the mc68hc705b16 serial bootstrap routine will first echo two blocks of four bytes at $00, as no data is programmed yet. if the data received is $00 for eprom locations or $ff for eeprom locations, no programming in the eprom and eeprom1 takes place, and the contents of the accessed location are returned as a prompt. the entire eprom/ eeprom memory can be read in this fashion (serial dump). warning: when using this function with a programmed device, the device must be placed into ram/eprom/eeprom serial bootstrap mode without eprom erase check (pd4 = 1). serial ram loading and execute can be accomplished in this mode. a ram byte will be written if the address sent by the host in the serial protocol points to the ram. ram bytes $008b?$00e3 and $0250?$02ed are available for user test programs. a 10-byte stack resides at the top of rami, allowing, for exampl e, one interrupt and two sub-routine levels. the ram addresses between $0050 and $008a are used by the loader and are therefore not available to the user during serial loading/executing. if the sec bit is at ?1?, program execution is triggered by sending a negative (bit 7 set) high address; execution starts at address xadr ($008b). in the ram bootloader mode, all interrupt vect ors are mapped to pseudo-vectors in ram (see ta b l e e - 5 ). this allows programmers to use their own service-routine addresses. each pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors, because an explicit jump (jmp) opcode is needed to cause the desired jump to the user?s service routine address. table e-5 bootstrap vector targets in ram vector targets in ram sci interrupt $02ee timer overflow $02f1 timer output compare $02f4 timer input capture $02f7 irq $02fa swi $02fd
mc68HC05B6 rev. 4.1 freescale e-19 mc68hc705b16 14 e.4.4 ram parallel bootstrap the program first checks the state of the security bit. if the sec bit is active, i.e. ?0?, the program will not enter the ram bootstrap mode and the r ed led will flash. otherwise the ram bootstrap program will start loading the ram with external data (e.g. from a 2564 or 2764 eprom). before loading a new byte the state of the pd4/an4 pin is che cked. if this pin goes to level ?0?, or if the ram is full, then control is given to the loaded program at address $0050. see figure e-3 and figure e-4 . if the data is supplied by a parallel interface, handshaking will be provided by pc5 and pc6 according to figure e-9 . if the data comes from an external eprom, the handshake can be disabled by connecting together pc5 and pc6. figure e-10 provides a schematic diagram of a circuit that can be used to load the ram with short test programs. up to 8 programs can be loaded in turn from the eprom. selection is accomplished by means of the switches con nected to the eprom higher address lines (a8 through a10). if the user program sets pc0 to le vel ?1?, this will disable the external eprom, thus rendering both port a output and port b input available. the eprom parallel bootstrap loader schematic can also be used ( figure e-7 ), provided vpp is at v dd level. the high order address lines will be at zero. the leds will stay off. figure e-9 parallel ram loader timing diagram t adr t dhr address data t cr pd4 t exr max t ho t hi max pc5 out pc6 in t adr max (address to data delay; pc6=pc5) 16 machine cycles t dhr min (data hold time) 4 machine cycles t cr (load cycle time; pc6=pc5) 49 machine cycles t ho (pc5 handshake out delay) 5 machine cycles t hi max (pc6 handshake in, data hold time) 10 machine cycles t exr max (max delay for transition to be recognis ed during this cycle; pc6=pc5 30 machine cycles 1 machine cycle = 1/(2f 0 (xtal))
freescale e-20 mc68HC05B6 rev. 4.1 mc68hc705b16 14 e.4.4.1 jump to st art of ram ($0050) pd4 must be high during the first 49 program cycles and pulled low before the 68th cycle for immediate jump execution at address $0050. figure e-10 ram parallel bootstrap schematic diagram pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb6 pb7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 vdd tcap2 tcmp2 tcmp1 plmb plma sclk tdo rdi vrh vrl pd7 pd6 pd5 pd3 pd2 pd1 pd0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 nc osc1 osc2 tcap1 irq reset pd4 vpp6 vss a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 gnd oe a8 a9 a10 a11 a12 ce vcc pgm vpp 20 2 25 24 23 14 22 10 9 8 7 6 5 4 1262728 21 12 13 15 16 17 18 19 11 3 +5v 3 x 4.7k ? +5v 16 x 100k ? 1 2 p1 gnd +5v 100 f 22pf 4.0 mhz 1n914 1k ? 1.0 f 22pf 100k ? 1n914 reset run 0.01 f u1 2764 +5v 18 x 100 k ? + + nc vpp1 u2 mc68hc705b16 mcu (socket)
mc68HC05B6 rev. 4.1 freescale e-21 mc68hc705b16 14 e.5 absolute maximum ratings note: this device contains circuitry designed to protect against damage due to high electrostatic voltages or electric fields. however, it is recommended that normal precautions be taken to avoid the application of any voltages higher than those given in the maximum ratings table to this high impedance circuit. for maximum reliability all unused inputs should be tied to either v ss or v dd . table e-6 absolute maximum ratings rating symbol value unit supply voltage (1) (1) all voltages are with respect to v ss . v dd ? 0.5 to +7.0 v input voltage (except v pp1 and v pp6 )v in v ss ? 0.5 to v dd + 0.5 v input voltage ? self-check mode (irq pin only) v in v ss ? 0.5 to 2v dd + 0.5 v operating temperature range ? standard (mc68hc705b16) ? extended (mc68hc705b16c) ? industrial (mc68hc705b16v) ? automotive (mc68hc705b16m) t a t l to t h 0 to +70 ?40 to +85 ?40 to +105 ?40 to +125 c storage temperature range t stg ? 65 to +150 c current drain per pin (excluding vdd and vss) (2) ? source ? sink (2) maximum current drain per pin is for one pin at a time, limited by an external resistor. i d i s 25 45 ma ma
freescale e-22 mc68HC05B6 rev. 4.1 mc68hc705b16 14 e.6 dc electrical characteristics table e-7 dc electrical characteristics for 5v operation (v dd = 5 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic (1) (1) all i dd measurements taken with suitable deco upling capacitors across the power suppl y to suppress the transient switching currents inherent in cmos designs (see section 2). symbol min typ (2) (2) typical values are at mid point of voltage range and at 25 c only. max unit output voltage i load = ? 10 a i load = +10 a v oh v ol v dd ? 0.1 ? ? ? ? 0.1 v output high voltage (i load = 0.8ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2 output high voltage (i load = 1.6ma) tdo, sclk, plma, plmb v oh v oh v dd ? 0.8 v dd ? 0.8 v dd ? 0.4 v dd ? 0.4 ? ? v output low voltage (i load = 1.6ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 1.6ma) reset v ol v ol ?0.1 0.4 0.4 1 v input high voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset , tcap1, tcap2, rdi v ih 0.7v dd ?v dd v input low voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, i rq , reset , tcap1, tcap2, rdi v il v ss ?0.2v dd v supply current (3) run (sm = 0) (see figure 11-1 ) run (sm = 1) (see figure 11-2 ) wait (sm = 0) (see figure 11-3 ) wait (sm = 1) (see figure 11-4 ) stop 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 105 (industrial) ? 40 to 125 (automotive) (3) run and wait i dd : measured using an external square-wave clock source (f osc = 4.2mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all ports configured as inputs; v il = 0.2 v and v ih =v dd ? 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance. i dd i dd i dd i dd i dd i dd i dd i dd ? ? ? ? ? ? ? ? 5.0 1.0 1.5 0.9 2 ? ? ? 6 1.5 2 1 10 20 60 60 ma ma ma ma a a a a high-z leakage current pa0?7, pb0?7, pc0?7, tdo, reset , sclk i il ? 0.2 1 a input current port b and port c pull-down (v in =v ih )i rpd 80 a input current (0 to 70) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ? 0.2 1 a input current (? 40 to 125) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ?? 5 a capacitance ports (as input or output), reset , tdo, sclk irq , tcap1, tcap2, osc1, rdi pd0/an0?pd7/an7 (a/d off) pd0/an0?pd7/an7 (a/d on) c out c in c in c in ? ? ? ? ? ? 12 22 12 8 ? ? pf pf pf pf
mc68HC05B6 rev. 4.1 freescale e-23 mc68hc705b16 14 table e-8 dc electrical characteristics for 3.3v operation (v dd = 3.3vdc 10%, v ss = 0vdc, t a = t l to t h ) characteristic (1) symbol min typ (2) max unit output voltage i load = ? 10 a i load = +10 a v oh v ol v dd ? 0.1 ? ? ? ? 0.1 v output high voltage (i load = 0.8ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2 output high voltage (i load = 1.6ma) tdo, sclk, plma, plmb v oh v oh v dd ? 0.3 v dd ? 0.3 v dd ? 0.1 v dd ? 0.1 ? ? v output low voltage (i load = 1.6ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 1.6ma) reset v ol v ol ?0.1 0.2 0.4 0.6 v input high voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset , tcap1, tcap2, rdi v ih 0.7v dd ?v dd v input low voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset , tcap1, tcap2, rdi v il v ss ?0.2v dd v supply current (3) run (sm = 0) (see figure 11-1 ) run (sm = 1) (see figure 11-2 ) wait (sm = 0) (see figure 11-3 ) wait (sm = 1) (see figure 11-4 ) stop 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 105 (industrial) ? 40 to 125 (automotive) i dd i dd i dd i dd i dd i dd i dd i dd ? ? ? ? ? ? ? ? 2.0 0.8 1.0 0.4 1 ? ? ? 3 1 1.5 0.5 10 10 40 40 ma ma ma ma a a a a high-z leakage current pa0?7, pb0?7, pc0?7, tdo, reset , sclk i il ? 0.2 1 a input current port b and port c pull-down (v in =v ih )i rpd 80 a input current (0 to 70) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ? 0.2 1 a input current (? 40 to 125) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ?? 5 a capacitance ports (as input or output), reset , tdo, sclk irq , tcap1, tcap2, osc1, rdi pd0/an0?pd7/an7 (a/d off) pd0/an0?pd7/an7 (a/d on) c out c in c in c in ? ? ? ? ? ? 12 22 12 8 ? ? pf pf pf pf (1) all i dd measurements taken with suitable decoupling capacitors ac ross the power supply to suppr ess the transient switching currents inherent in cmos designs (see section 2). (2) typical values are at mid point of voltage range and at 25 c only.
freescale e-24 mc68HC05B6 rev. 4.1 mc68hc705b16 14 (3) run and wait i dd : measured using an external square-wave clock source (f osc = 2.0mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all ports configured as inputs; v il = 0.2 v and v ih =v dd ? 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance.
mc68HC05B6 rev. 4.1 freescale e-25 mc68hc705b16 14 e.7 a/d converter characteristics table e-9 a/d characteristics for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 ? bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) ? 0.5 lsb quantization error uncertainty due to converter resolution ? 0.5 lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors ? 1lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss ? 0.1 v rh v ? v r (1) (1) performance verified down to 2.5v ? vr, but accuracy is tested and guaranteed at ? vr = 5v 10%. minimum difference between v rh and v rl 3?v conversion time total time to perform a single analog to digital conversion a. external clock (osc1, osc2) b. internal rc oscillator ? ? 32 32 t cyc s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conversion result when v in = v rl 00 ? hex full scale reading conversion result when v in = v rh ?ffhex sample acquisition time analog input acquisition sampling a. external clock (osc1, osc2) b. internal rc oscillator (2) (2) source impedances greater than 10k ? will adversely affect internal charging time during input sampling. ? ? 12 12 t cyc s sample/hold capacitance input capacitance on pd0/an0?pd7/an7 ? 12 pf input leakage (3) (3) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input cu rrent to a/d channel w ill be dependent on external source impedance (see figure 8-2 ). input leakage on a/d pins pd0/an0?pd7/an7, vrl, vrh ? 1 a
freescale e-26 mc68HC05B6 rev. 4.1 mc68hc705b16 14 table e-10 a/d characteristics for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 ? bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) ? 1lsb quantization error uncertainty due to converter resolution ? 1lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors ? 2lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss ? 0.1 v rh v ? v r minimum difference between v rh and v rl 3?v conversion time total time to perfor m a single analog to digital conversion internal rc oscillator ? 32 s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conv ersion result when v in = v rl 00 ? hex full scale reading conversion result when v in = v rh ?ffhex sample acquisition time analog input acquisition sampling internal rc oscillator (1) ?12 s sample/hold capacitance input capacitance on pd0/an0?pd7/an7 ? 12 pf input leakage (2) input leakage on a/d pins pd0/an0?pd7/an7, vrl, vrh ? 1 a (1) source impedances greater than 10k ? will adversely affect internal charging time during input sampling. (2) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input current to a/d channel will be dependent on external source impedance (see figure 8-2 ).
mc68HC05B6 rev. 4.1 freescale e-27 mc68hc705b16 14 e.8 control timing table e-11 control timing for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc ? dc 4.2 4.2 mhz mhz internal operating frequency (f osc /2) using crystal using external clock f op f op dc dc 2.1 2.1 mhz mhz cycle time (see figure 9-1 )t cyc 480 ? ns crystal oscillator start-up time (see figure 9-1 )t oxov ? 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms rc oscillator stabilization time t adrc 5 s a/d converter stabilization time t adon 500 s external reset input pulse width t rl 1.5 ? t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 ? ? t cyc t cyc watchdog reset output pulse width t dogl 1.5 ? t cyc watchdog time-out t dog 6144 7168 t cyc eeprom byte erase time 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 105 (industrial) ? 40 to 125 (automotive) t era t era t era t era 10 10 10 10 ? ? ? ? ms ms ms ms eeprom byte program time (1) 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 105 (industrial) ? 40 to 125 (automotive) (1) for bus frequencies less than 2 mhz, the inte rnal rc oscillator should be used when programming the eeprom. t prog t prog t prog t prog 10 10 15 20 ? ? ? ? ms ms ms ms timer (see figure e-11 ) resolution (2) input capture pulse width input capture pulse period (2) since a 2-bit prescaler in the time r must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. t resl t th , t tl t tltl 4 125 ? (3) (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . ? ? ? t cyc ns t cyc interrupt pulse width (edge-triggered) t ilih 125 ? ns interrupt pulse period t ilil ? (4) (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . ?t cyc osc1 pulse width (5) (5) t oh and t ol should not total less than 238ns. t oh , t ol 90 ? ns write/erase endurance (6)(7) (6) at a temperature of 85 c ? 10000 cycles data retention (6)(7) (7) refer to reliability monitor report (current quar terly issue) for current failure rate information. ? 10 years
freescale e-28 mc68HC05B6 rev. 4.1 mc68hc705b16 14 table e-12 control timing for 3.3v operation (v dd = 3.3vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc ? dc 2.0 2.0 mhz mhz internal operating frequency (f osc /2) using crystal using external clock f op f op ? dc 1.0 1.0 mhz mhz cycle time (see figure 9-1 )t cyc 1000 ? ns crystal oscillator start-up time (see figure 9-1 )t oxov ?100ms stop recovery start-up time (crystal oscillator) t ilch 100 ms rc oscillator stabilization time t adrc 5 s a/d converter stabilization time t adon 500 s external reset input pulse width t rl 1.5 ? t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 ? ? t cyc t cyc watchdog reset output pulse width t dogl 1.5 ? t cyc watchdog time-out t dog 6144 7168 t cyc eeprom byte erase time 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 105 (industrial) ? 40 to 125 (automotive) t era t era t era t era 30 30 30 30 ? ? ? ? ms ms ms ms eeprom byte program time (1) 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 105 (industrial) ? 40 to 125 (automotive) t prog t prog t prog t prog 30 30 30 30 ? ? ? ? ms ms ms ms timer (see figure e-11 ) resolution (2) input capture pulse width input capture pulse period t resl t th , t tl t tltl 4 250 ? (3) ? ? ? t cyc ns t cyc interrupt pulse widt h (edge-triggered) t ilih 250 ? ns interrupt pulse period t ilil ? (4) ?t cyc osc1 pulse width (5) t oh , t ol 200 ? ns write/erase endurance (6)(7) ? 10000 cycles data retention (6)(7) ?10years (1) for bus frequencies less than 2 mhz, the internal rc oscillator should be used when programming the eeprom. (2) since a 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . (5) t oh and t ol should not total less than 500ns. (6) at a temperature of 85 c (7) refer to reliability monitor report (current quar terly issue) for current failure rate information.
mc68HC05B6 rev. 4.1 freescale e-29 mc68hc705b16 14 e.9 eprom electrical characteristics figure e-11 timer relationship table e-13 dc electrical characteristics for 5v operation (v dd = 5 vdc 10%, v ss = 0 vdc, t a = 25 c) characteristic (1) (1) all i dd measurements taken with suitable decoupling capa citors across the power supply to suppress the transient switching currents inherent in cmos designs (see section 2). symbol min typ (2) (2) typical values are at mid point of voltage range and at 25 c only. max unit eprom absolute maximum voltage programming voltage programming current read voltage v pp6 max v pp6 i pp6 v pp6r v dd 15 ? v dd ? 15.5 50 v dd 18 16 64 v dd v v ma v table e-14 control timing for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = 25 c) characteristic symbol min max unit eprom programming time t prog 520ms table e-15 control timing for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = 25 c) characteristic symbol min max unit eprom programming time t prog 520ms external signal (tcap1, tcap2) t tltl t th t tl
freescale e-30 mc68HC05B6 rev. 4.1 mc68hc705b16 14
mc68HC05B6 rev. 4.1 freescale f-1 mc68hc705b16n 14 f mc68hc705b16n the mc68hc705b16n is a device similar to the mc68HC05B6, but with increased ram and 15 kbytes of eprom instead of 6 kbytes of rom. in addition, the self-check routines available in the mc68HC05B6 are replaced by bootstrap firmware. the mc68hc705b16n is an otprom (one-time programmable rom) version of the mc 68hc05b16, meaning that once the application program has been loaded in the eprom it ca n never be erased. the entire mc68HC05B6 data sheet applies to the mc68hc705b16n, with the exceptions outlined in this appendix. the mc68hc705b16n is a new device identical to the mc68hc705b16 in its memory map and functionality, except for the following: bootloader reset pulse width reset twice issue electrical characteristics on the mc68hc705b16 there was a requirement to reset the device a second time after power-on. on the mc68hc705b16n this reset twice action is now not required. the interrupt service routine for the vect or at address $3ff0?$3ff1 is no longer required, as the vector will never be fetched. however, the interrupt service routine and vector contents required for the mc68hc705b16 (see section e , page e?1) can also be kept on the mc68hc705b16n with no detri mental effect, although they will never be used. 213 214 215 216 217
freescale f-2 mc68HC05B6 rev. 4.1 mc68hc705b16n 14 f.1 features 15 kbytes eprom 352 bytes of ram 576 bytes bootstrap rom simultaneous programming of up to 8 bytes of eprom optional pull-down resistors available on all port b and port c pins 52-pin plcc and 64-pin qfp packages note: the electrical characteristics of the mc68HC05B6 as provided in section 11 do not apply to the mc68hc705b16n. data specific to the mc68hc705b16n can be found in this appendix. figure f-1 mc68hc705b16n block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp1 256 bytes eeprom charge pump 2 / 32 plma d/a plmb d/a 8-bit 15168 bytes eprom 352 bytes static ram 576 bytes vpp6 bootstrap rom 218 219 220 221 222
mc68HC05B6 rev. 4.1 freescale f-3 mc68hc705b16n 14 figure f-2 memory map of the mc68hc705b16n port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $3ff0?1 stack ram1 (176 bytes) $0250 $0200 $3e00 $0050 port a data direction register port b data direction register port c data direction register e/eeprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f page 0 user eprom (48 bytes) user eprom (15104 bytes) bootstrap rom11 (496 bytes) $0300 options register unprotected (31 bytes) protected (224 bytes) eeprom (256 bytes) $0101 $0120 $0100 options register reserved mc68hc705b16 registers ram11 (176 bytes) $3dfe $3dff mask option register mask option register $3dfe bootstrap rom1 (80 bytes) user vectors (14 bytes) $3ff2?3 sci timer overflow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $3ff4?5 $3ff6?7 $3ff8?9 $3ffa?b $3ffc?d $3ffe?f 223 224 225 226 227
freescale f-4 mc68HC05B6 rev. 4.1 mc68hc705b16n 14 table f-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 undefined port b data (portb) $0001 undefined port c data (portc) $0002 pc2/ eclk undefined port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 undefined port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eprom/eeprom/eclk control $0007 e6lat e6pgm eclk e1era e1lat e1pgm 0000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl undefined sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 undefined input capture high 1 $0014 undefined input capture low 1 $0015 undefined output compare high 1 $0016 undefined output compare low 1 $0017 undefined timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c undefined input capture low 2 $001d undefined output compare high 2 $001e undefined output compare low 2 $001f undefined options (optr) (3) $0100 ee1p sec not affected mask option register (mor) (4) $3dfe rtim rwat wwat pbpd pcpd not affected (1) this bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent upon t he mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) this register is implemented in eeprom; theref ore reset has no effect on the individual bits. (4) this register is implemented in eprom; theref ore reset has no effect on the individual bits. 228 229 230 231 232
mc68HC05B6 rev. 4.1 freescale f-5 mc68hc705b16n 14 f.2 external clock when using an external clock the osc1 and os c2 pins should be driven in antiphase (see figure d-2 ). the t oxov or t ilch specifications (see section f.9 ) do not apply when using an external clock input. the equivalent specification of the external clock source should be used in lieu of t oxov or t ilch . f.3 reset pin when the oscillator is running in a stable condition, the mcu is reset when a logic zero is applied to the reset input for a minimum peri od of 3.0 machine cycles (t cyc ). for more information see section 9.1.3 . f. 4 ep ro m the mc68hc705b16n memory map is given in figure f-2 . the device has a total of 15168 bytes of eprom (including 14 bytes for user vectors) and 256 bytes of eeprom. the eprom array is supplied by the vpp6 pin in both read and program modes. typically the user?s software would be loaded into a programming board where v pp6 is controlled by one of the bootstrap loader routines. it would then be placed in an application where no programming occurs. in this case the vpp6 pi n should be hardwired to v dd . warning: a minimum v dd voltage must be applied to the vpp6 pin at all times, including power-on. failure to do so could result in permanent damage to the device. unless otherwise stated, eprom programmi ng is guaranteed at ambient (25 c) temperature only. f.4.1 eprom read operation the execution of a program in the eprom addres s range or a load from the eprom are both read operations. the e6lat bit in the eprom/eepr om control register should be cleared to ?0? which automatically resets the e6pgm bit. in this way the eprom is read like a normal rom. reading the eprom with the e6lat bit set will gi ve data that does not correspond to the actual memory content. as interrupt vectors are in eprom, they will not be loaded when e6lat is set. similarly, the bootstrap rom routines cannot be executed when e6lat is set. in read mode, the vpp6 pin must be at the v dd level. when entering the stop mode, the eprom is automatically set to the read mode. note: an erased byte reads as $00. 233 234 235 236 237
freescale f-6 mc68HC05B6 rev. 4.1 mc68hc705b16n 14 f.4.2 eprom program operation typically the eprom will be programmed by the bootstrap routines resident in the on-chip rom. however, the user program can be used to program some eprom locations if the proper procedure is followed. in particular, the programming sequence must be running in ram, as the eprom will not be available for code execution while the e6lat bit is set. the v pp6 switching must occur externally after the e6pgm bit is se t, for example under control of a signal generated on a pin by the programming routine. note: when the part becomes a prom, only the cumulative programming of bits to logic ?1? is possible if multiple programming is made on the same byte. to allow simultaneous programming of up to eight bytes, these bytes must be in the same group of addresses which share the same most signific ant address bits; only t he three least significant bits can change. f.4.3 eprom/eeprom/eclk control register e6lat ? eprom programming latch enable bit 1 (set) ? address and up to eight data bytes can be latched into the eprom for further programming providing the e6pgm bit is cleared. 0 (clear) ? data can be read from the epr om or firmware rom; the e6pgm bit is reset to zero when e6lat is ?0?. stop, power-on and external reset clear the e6lat bit. note: after the t era1 erase time or t prog1 programming time, the e6lat bit has to be reset to zero in order to clear the e6pgm bit. e6pgm ? eprom program enable bit this bit is the eprom program enable bit. it can be set to ?1? to enable programming only after e6lat is set and at least one byte is written to the eprom. it is not possible to clear this bit using software but clearing e6 lat will always clear e6pgm. note: the e6pgm bit can never be set while the e6lat bit is at zero. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eprom/eeprom/eclk control $0007 e6lat e6pgm eclk e1era e1lat e1pgm 0000 0000 238
mc68HC05B6 rev. 4.1 freescale f-7 mc68hc705b16n 14 eclk see section 4.3 . e1era ? eeprom erase/programming bit providing the e1lat and e1pgm bits are at logic one, this bit indicates whether the access to the eeprom is for erasing or programming purposes. 1 (set) ? an erase operation will take place. 0 (clear) ? a programming operation will take place. once the program/erase eeprom address has been selected, e1era cannot be changed. e1lat ? eeprom programming latch enable bit 1 (set) ? address and data can be latched into the eeprom for further program or erase operations, providing the e1pgm bit is cleared. 0 (clear) ? data can be read from t he eeprom. the e1era bit and the e1pgm bit are reset to zero when e1lat is ?0?. stop, power-on and external reset clear the e1lat bit. note: after the t era1 erase time or t prog1 programming time, the e1lat bit has to be reset to zero in order to clear the e1era bit and the e1pgm bit. e1pgm ? eeprom charge pump enable/disable 1 (set) ? internal charge pump generator switched on. 0 (clear) ? internal charge pump generator switched off. when the charge pump generator is on, the resulti ng high voltage is applied to the eeprom array. this bit cannot be set before the data is select ed, and once this bit has been set it can only be cleared by clearing the e1lat bit. a summary of the effects of setti ng/clearing bits 0, 1 and 2 of t he control register are given in ta bl e f - 3 . note: the e1pgm and e1era bits are cleared when the e1lat bit is at zero. table f-2 eprom control bits description e6lat e6pgm description 0 0 read/execute in eprom 1 0 ready to write address/data to eprom 1 1 programming in progress
freescale f-8 mc68HC05B6 rev. 4.1 mc68hc705b16n 14 f.4.4 mask option register rtim ? reset time this bit can modify the time t porl , where the reset pin is kept low after a power-on reset. 1 (set) ? t porl = 16 cycles. 0 (clear) ? t porl = 4064 cycles. rwat ? watchdog after reset this bit can modify the status of the watchdog counter after reset. usually, the watchdog system is disabled after power-on or external reset but when this bit is set, it will be active immediately after the following resets (except in bootstrap mode). wwat ? watchdog during wait mode this bit can modify the status of the watchdog counter in wait mode. normally, the watchdog system is disabled in wait mode but when this bit is set, the watchdog will be active in wait mode. pbpd ? port b pull-down this bit, when programmed, connects a resistive pull-down on each pin of port b. this pull-down, r pd , is active on a given pin only while it is an input. table f-3 eeprom control bits description e1era e1lat e1pgm description 0 0 0 read condition 0 1 0 ready to load address/data for program/erase 0 1 1 byte programming in progress 1 1 0 ready for byte erase (load address) 1 1 1 byte erase in progress address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset mask option register (mor) (1) (1) this register is implemented in eprom; ther efore reset has no effect on the individual bits. $3dfe rtim rwat wwat pbpd pcpd not affected
mc68HC05B6 rev. 4.1 freescale f-9 mc68hc705b16n 14 pcpd ? port c pull-down this bit, when programmed, connects a resistive pul l-down on each pin of port c. this pull-down, r pd , is active on a given pin only while it is an input. f.4.5 eeprom options register (optr) ee1p ? eeprom protect bit in order to achieve a higher degr ee of protection, the eeprom is effectively split into two parts, both working from the vpp1 charge pump. part 1 of the eeprom array (32 bytes from $0100 to $011f) cannot be protected; part 2 (224 bytes from $0120 to $01ff) is protected by the ee1p bit in the options register. 1 (set) ? part 2 of the eeprom array is not protected; all 256 bytes of eeprom can be accessed for any read, erase or programming operations. 0 (clear) ? part 2 of the eeprom array is protected; any attempt to erase or program a location will be unsuccessful. when this bit is set to 1 (erased), the protection will remain until the next power-on or external reset. ee1p can only be written to ?0? when the e1lat bit in the eeprom c ontrol register is set. note: the eeprom1 protect function is disabled while in bootstrap mode. sec ? secure bit this bit allows the eprom and eeprom1 to be secu red from external access. when this bit is in the erased state (set), the eprom and eepr om1 content is not secured and the device may be used in non user mode. when the sec bit is programmed to ?zero?, the eprom and eeprom1 content is secured by prohibiting entry to the non user mode. to deactivate the secure bit, the eprom has to be erased by exposure to a high density ultraviolet light, and the device has to be entered into the eprom erase verification mode with pd1 set. when the sec bit is changed, its new value will have no effect until the next power-on or external reset. 1 (set) ? eeprom/eprom not protected. 0 (clear) ? eeprom/eprom protected. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset options (optr) (1) (1) this register is implemented in eeprom; theref ore reset has no effect on the individual bits. $0100 ee1p sec not affected
freescale f-10 mc68HC05B6 rev. 4.1 mc68hc705b16n 14 f.5 bootstrap mode oscillator divide-by-two is forced in bootstrap mode. the 432 bytes of self-check firmware on the mc68HC05B6 are replaced by 576 bytes of bootstrap firmware. a detailed description of the modes of operation within bootstrap mode is given below. the bootstrap program in mask rom address locations $0200 to $024f and $3e00 to $3fef can be used to program the eprom and the eeprom, to check if the eprom is erased or to load and execute data in ram. after reset, while going to the bootstrap mode, the vector located at address $3fee and $3fef (reset ) is fetched to start execution of the boot strap program. to place the part in bootstrap mode, the irq pin should be at 2xv dd with the tcap1 pin ?high? during transition of the reset pin from low to high. the hold time on the irq and tcap1 pins is two clock cycles after the external reset pin is brought high. when the mc68hc705b16n is placed in the bootstrap mode, the bootstrap reset vector will be fetched and the bootstrap firmware will start to execute. ta b l e f - 4 shows the conditions required to enter each level of bootstrap mode on the rising edge of reset . the bootstrap program will first copy part of it self in ram (except ?ram parallel load?), as the program cannot be executed in rom during verifica tion/programming of the eprom. it will then set the tcmp1 output to a logic high level, unl ike the mc68HC05B6 which keeps tcmp1 low. this can be used to distinguish between the two circuits and, in particula r, for selection of the vpp level and current capability. table f-4 mode of operation selection irq pin tcap1 pin pd1 pd2 pd3 pd4 mode v ss to v dd v ss to v dd x x x x single chip 2xv dd v dd 0 0 0 0 erased eprom verification 2xv dd v dd 0010eprom verification; 2xv dd v dd 1000 eprom verification; erase eeprom; eprom/eeprom parall el program/verify 2xv dd v dd 1010 erased eprom verification; erase eeprom; eprom parallel pr ogram/verify (no e 2 ) 2xv dd v dd 1 0 0 1 jump to start of ram ($0051); sec bit = non active 2xv dd v dd x011 serial ram load/execute ? simila r to mc68HC05B6 but can fill ram i and ii x = don?t care
mc68HC05B6 rev. 4.1 freescale f-11 mc68hc705b16n 14 figure f-3 modes of operation flow chart (1 of 2) irq at 2xv dd ? red led on tcap1=v dd ? sec bit active? pd3 set? user mode non-user mode n y y y n y n n pd4 set? n y n jump to ram ($0051) pd1 set? pd1 set? y red led on n eprom erased? n n y green led on y verify eprom d sec bit active? pd3 set? y sec bit active? n y eprom verified? red led on n y serial ram load/execute red led on n erased eprom verification green led on y y reset erased eprom verification eprom verify pd2 set? non-user mode y n pd2 set? non-user mode y n
freescale f-12 mc68HC05B6 rev. 4.1 mc68hc705b16n 14 figure f-4 modes of operation flow chart (2 of 2) go to $300 (eprom only) pd3 set? red led on go to $100 (eprom and eeprom) y n green led on eeprom erased? n d eeprom byte erase and verify data verified? y parallel program and verify parallel program y n
mc68HC05B6 rev. 4.1 freescale f-13 mc68hc705b16n 14 f.5.1 erased eprom verification if a non $00 byte is detected, the red led wi ll be turned on and the routine will stop (see figure f-3 and figure f-4 ). only when the whole eprom content is verified as erased will the green led be turned on. pd1 is then checked. if pd1=0, th e bootstrap program stops here and no programming occurs until such time as a high level is se nsed on pd1. if pd1 = 1, the bootstrap program proceeds to erase the eeprom1 for a nominal 2.5 seconds (4.0 mhz crystal). it is then checked for complete erasure; if any eeprom byte is not erased, the program will stop before erasing the sec byte. when both eprom and eeprom1 are completely erased and the security bit is cleared the programming operation can be performed . a schematic diagram of the circuit required for erased eprom verification is shown in figure f-8 . f.5.2 eprom/eeprom parallel bootstrap within this mode there are various subsections wh ich can be utilised by correctly configuring the port pins shown in ta b l e f - 4 . the erased eprom verification program will be executed first as described in section f.5.1 . the eprom programming time is set to 10 milliseconds with the bootstrap program and verify for the eprom taking approximately 15 seconds. the eprom will be loaded in increasing address order with non eprom segments being skipped by the loader. simultaneous programming is performed by reading eight bytes of data before actual programming is performed, thus dividing the loading time of the internal eprom by 8. if any block of 8 eprom bytes or 1 eeprom byte of data is in the erased state, no programming takes place, thus speeding up the execution time. parallel data is entered through port a, while the 15-bit address is output on port b, pc0 to pc4 and tcmp1 and tcmp2. if the data comes fr om an external eprom, the handshake can be disabled by connecting together pc5 and pc6. if the data is supplied by a parallel interface, handshake will be provided by pc5 and pc6 according to the timing diagram of figure f-6 (see also figure f-7 ). during programming, the green led will flash at about 3 hz. upon completion of the programming operat ion, the eprom and eeprom1 content will be checked against the external data source. if programming is verified the green led will stay on, while an error will cause the red led to be turned on. figure f-7 is a schematic diagram of a circuit which can be used to program the eprom or to load and execute data in the ram. note: the entire eprom and eeprom1 can be load ed from the external source; if it is desired to leave a segment undisturbed, t he data for this segment should be all $00s for eprom data and all $ffs for eeprom1 data.
freescale f-14 mc68HC05B6 rev. 4.1 mc68hc705b16n 14 figure f-5 timing diagram with handshake figure f-6 parallel eprom loader timing diagram data read data read address hdsk out (pc5) data hdsk in (pc6) f29 t cooe t ade t dhe address data t ade t dhe t ade t dhe t ade t dhe t cooe t cooe t cdde t ade max (address to data delay) 5 machine cycles t dha min (data hold time) 14 machine cycles t cooe (load cycle time) 117 machine cycles < t cooe < 150 machine cycles t cdde (programming cycle time) t cooe + t prog (10 ms nominal for eprom; 10ms for eeprom1)) 1 machine cycle = 1/(2f 0 (xtal))
mc68HC05B6 rev. 4.1 freescale f-15 mc68hc705b16n 14 figure f-7 eprom parallel bootstrap schematic diagram vcc 28 1 vpp pgm 27 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 vdd osc1 osc2 tcap1 irq reset vss a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 gnd oe 14 22 10 9 8 7 6 5 4 26 12 13 15 16 17 18 19 11 3 +5v 1 2 p1 gnd +5v 100 f 22pf 4.0 mhz 1n914 1k ? 1.0 f 22pf 100k ? 1n914 reset run 0.01 f tdo sclk rdi vrl tcap2 pd7 pd6 pd5 pd3 pd2 pd1 pd0 pd4 +5v 3 v pp vpp6 pc7 pc5 pc4 pc3 pc2 pc1 pc0 pc6 24 21 23 2 a9 a8 a10 a12 ce a11 a12 a11 a10 a9 a8 hdsk out hdsk in short circuit if handshake not used 100 k ? nc tcmp1 tcmp2 plma plmb 470 ? 470 ? red led green led 4k7 ? 4k7 ? 12 k ? bc239c bc309c 10k ? 27c256 + + vrh red led ? programming failed green led ? programming ok 25 1nf 1n5819 1 k ? + eprom green led ? eprom erased 47 f + erase verify & boot eprom check vpp1 red led ? eprom not erased boot erase check a13 20 mc68hc705b16n mcu a14 note: this circuit is recommended for programming only at 25 c and not for use in the end application, or at temperatures other than 25 c. if used in the end application, vpp6 should be tied to vdd to avoid damaging the device. eprom verify erase check & boot (eprom only) erase check & boot (eprom & eeprom)
freescale f-16 mc68HC05B6 rev. 4.1 mc68hc705b16n 14 f.5.3 serial ram loader this mode is similar to the ram load/exec ute program for the mc68HC05B6 described in section 2.2 , with the additional features listed below. ta b l e f - 4 shows the entry conditions required for this mode. if the first byte is less than $b0, the bootloader behaves exactly as the mc68HC05B6, i.e. count byte followed by data stored in $0050 to $00ff. if the count byte is larger than ram i (176 bytes) then the code continues to fill ra m ii. in this case the count byte is ignored and the program execution begins at $0051 once the total ram area is filled or if no data is received for 5 milliseconds. the user must take care when using branches or jumps as his code will be relocated in ram i and ii. if the user intends to use the stack in his prog ram, he should send nop? s to fill the desired stack area. in the ram bootloader mode, all interrupt vect ors are mapped to pseudo-vectors in ram (see ta b l e f - 5 ). this allows programmers to use their own service-routine addresses. each pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors, because an explicit jump (jmp) opcode is n eeded to cause the desired jump to the users service-routine address. f.5.3.1 jump to start of ram ($0051) the jump to start of ram program will be executed when the device is brought out of reset with pd1 and pd4 at ?1? and pd2 and pd3 at ?0?. table f-5 bootstrap vector targets in ram vector targets in ram sci interrupt $0063 timer overflow $0060 timer output compare $005d timer input capture $005a irq $0057 swi $0054
mc68HC05B6 rev. 4.1 freescale f-17 mc68hc705b16n 14 figure f-8 ram load and execute schematic diagram green led ? programming ended flashing green led ? programming 40 vpp6 pc7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 vdd osc1 osc2 tcap1 irq reset vss 1 2 p1 gnd +5v 1n914 1k ? 1.0 f 100k ? 1n914 reset run 0.01 f 3 v pp pc5 pc4 pc3 pc2 pc1 pc0 pc6 plma plmb 470 ? 470 ? red led green led + + vrh 22 f 22 f 22 f 2 x 3k ? 1 2 3 4 8 6 7 5 11 12 13 14 15 16 5 3 2 1 22 f rs232 connector max 232 +5v 9600 bd 8-bit no parity 19 18 20 21 50 52 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 14 13 12 5 4 43 44 45 46 47 48 49 23 2 1 51 22 8 10 41 7 vrl tcap2 tcmp1 tcmp2 sclk nc 10nf 47 f pd0 pd4 pd1 pd2 pd5 pd6 pd7 + + + + 22pf 4.0 mhz 22pf 4k7 ? 4k7 ? 12 k ? bc239c bc309c 10k ? 1nf 1n5819 1 k ? + serial boot 47 f + pd3 rdi tdo erase check red led ? eprom not erased green led ? eprom erased serial boot serial ram vpp1 3 mc68hc705b16n mcu (socket) jump to $51 ram load & execute load & execute note: a minimum v dd voltage must be applied to the vpp6 pin at all times, including power-on, as a lower voltage could damage the device. unless otherwise stated, eprom programming is guaranteed at ambient (25 c) temperature only
freescale f-18 mc68HC05B6 rev. 4.1 mc68hc705b16n 14 figure f-9 parallel ram loader timing diagram t adr t dhr address data t cr pd4 t exr max t ho t hi max pc5 out pc6 in t adr max (address to data delay; pc6=pc5) 16 machine cycles t dhr min (data hold time) 4 machine cycles t cr (load cycle time; pc6=pc5) 49 machine cycles t ho (pc5 handshake out delay) 5 machine cycles t hi max (pc6 handshake in, data hold time) 10 machine cycles t exr max (max delay for transition to be recognise d during this cycle; pc6=pc5 30 machine cycles 1 machine cycle = 1/(2f 0 (xtal))
mc68HC05B6 rev. 4.1 freescale f-19 mc68hc705b16n 14 f.6 absolute maximum ratings note: this device contains circuitry designed to protect against damage due to high electrostatic voltages or electric fields. however, it is recommended that normal precautions be taken to avoid the application of any voltages higher than those given in the maximum ratings table to this high impedance circuit. for maximum reliability all unused inputs should be tied to either v ss or v dd . table f-6 absolute maximum ratings rating symbol value unit supply voltage (1) (1) all voltages are with respect to v ss . v dd ? 0.5 to +7.0 v input voltage (except v pp1 and v pp6 )v in v ss ? 0.5 to v dd + 0.5 v input voltage ? self-check mode (irq pin only) v in v ss ? 0.5 to 2v dd + 0.5 v operating temperature range ? standard (mc68hc705b16n) ? extended (mc68hc705b16nc) ? industrial (mc68hc705b16nv) ? automotive (mc68hc705b16nm) t a t l to t h 0 to +70 ?40 to +85 ?40 to +105 ?40 to +125 c storage temperature range t stg ? 65 to +150 c current drain per pin (excluding vdd and vss) (2) ? source ? sink (2) maximum current drain per pin is for one pin at a time, limited by an external resistor. i d i s 25 45 ma ma
freescale f-20 mc68HC05B6 rev. 4.1 mc68hc705b16n 14 f.7 dc electrical characteristics table f-7 dc electrical characteristics for 5v operation (v dd = 5 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic (1) (1) all i dd measurements taken with suitable deco upling capacitors across the power suppl y to suppress the transient switching currents inherent in cmos designs (see section 2). symbol min typ (2) (2) typical values are at mid point of voltage range and at 25 c only. max unit output voltage i load = ? 10 a i load = +10 a v oh v ol v dd ? 0.1 ? ? ? ? 0.1 v output high voltage (i load = 0.8ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2 output high voltage (i load = 1.6ma) tdo, sclk, plma, plmb v oh v oh v dd ? 0.8 v dd ? 0.8 v dd ? 0.4 v dd ? 0.4 ? ? v output low voltage (i load = 1.6ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 1.6ma) reset v ol v ol ?0.1 0.4 0.4 1 v input high voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset , tcap1, tcap2, rdi v ih 0.7v dd ?v dd v input low voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, i rq , reset , tcap1, tcap2, rdi v il v ss ?0.2v dd v supply current (3) run (sm = 0) (see figure 11-1 ) run (sm = 1) (see figure 11.2 ) wait (sm = 0) (see figure 11-3 ) wait (sm = 1) (see figure 11-4 ) stop 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 105 (industrial) ? 40 to 125 (automotive) (3) run and wait i dd : measured using an external square-wave clock source (f osc = 4.2mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all ports configured as inputs; v il = 0.2 v and v ih =v dd ? 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance. i dd i dd i dd i dd i dd i dd i dd i dd ? ? ? ? ? ? ? ? 5.0 1.0 1.5 0.9 2 ? ? ? 6 1.5 2 1 10 20 60 100 ma ma ma ma a a a a high-z leakage current pa0?7, pb0?7, pc0?7, tdo, reset , sclk i il ? 0.2 1 a input current port b and port c pull-down (v in =v ih )i rpd 80 a input current (0 to 70) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ? 0.2 1 a input current (? 40 to 125) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ?? 5 a capacitance ports (as input or output), reset , tdo, sclk irq , tcap1, tcap2, osc1, rdi pd0/an0?pd7/an7 (a/d off) pd0/an0?pd7/an7 (a/d on) c out c in c in c in ? ? ? ? ? ? 12 22 12 8 ? ? pf pf pf pf
mc68HC05B6 rev. 4.1 freescale f-21 mc68hc705b16n 14 table f-8 dc electrical characteristics for 3.3v operation (v dd = 3.3vdc 10%, v ss = 0vdc, t a = t l to t h ) characteristic (1) symbol min typ (2) max unit output voltage i load = ? 10 a i load = +10 a v oh v ol v dd ? 0.1 ? ? ? ? 0.1 v output high voltage (i load = 0.8ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2 output high voltage (i load = 1.6ma) tdo, sclk, plma, plmb v oh v oh v dd ? 0.3 v dd ? 0.3 v dd ? 0.1 v dd ? 0.1 ? ? v output low voltage (i load = 1.6ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 1.6ma) reset v ol v ol ?0.1 0.2 0.4 0.6 v input high voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset , tcap1, tcap2, rdi v ih 0.7v dd ?v dd v input low voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset , tcap1, tcap2, rdi v il v ss ?0.2v dd v supply current (3) run (sm = 0) (see figure 11-1 ) run (sm = 1) (see figure 11-2 ) wait (sm = 0) (see figure 11-3 ) wait (sm = 1) (see figure 11-4 ) stop 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 105 (industrial) ? 40 to 125 (automotive) i dd i dd i dd i dd i dd i dd i dd i dd ? ? ? ? ? ? ? ? 2.0 0.8 1.0 0.4 1 ? ? ? 3 1 1.5 0.5 10 10 40 60 ma ma ma ma a a a a high-z leakage current pa0?7, pb0?7, pc0?7, tdo, reset , sclk i il ? 0.2 1 a input current port b and port c pull-down (v in =v ih )i rpd 80 a input current (0 to 70) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ? 0.2 1 a input current (? 40 to 125) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ?? 5 a capacitance ports (as input or output), reset , tdo, sclk irq , tcap1, tcap2, osc1, rdi pd0/an0?pd7/an7 (a/d off) pd0/an0?pd7/an7 (a/d on) c out c in c in c in ? ? ? ? ? ? 12 22 12 8 ? ? pf pf pf pf (1) all i dd measurements taken with suitable decoupling capacitors ac ross the power supply to suppr ess the transient switching currents inherent in cmos designs (see section 2). (2) typical values are at mid point of voltage range and at 25 c only.
freescale f-22 mc68HC05B6 rev. 4.1 mc68hc705b16n 14 (3) run and wait i dd : measured using an external square-wave clock source (f osc = 2.0mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all ports configured as inputs; v il = 0.2 v and v ih =v dd ? 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance.
mc68HC05B6 rev. 4.1 freescale f-23 mc68hc705b16n 14 f.8 a/d converter characteristics table f-9 a/d characteristics for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 ? bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) ? 0.5 lsb quantization error uncertainty due to converter resolution ? 0.5 lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors ? 1lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss ? 0.1 v rh v ? v r (1) (1) performance verified down to 2.5v ? vr, but accuracy is tested and guaranteed at ? vr = 5v 10%. minimum difference between v rh and v rl 3?v conversion time total time to perform a single analog to digital conversion a. external clock (osc1, osc2) b. internal rc oscillator ? ? 32 32 t cyc s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conversion result when v in = v rl 00 ? hex full scale reading conversion result when v in = v rh ?ffhex sample acquisition time analog input acquisition sampling a. external clock (osc1, osc2) b. internal rc oscillator (2) (2) source impedances greater than 10k ? will adversely affect internal charging time during input sampling. ? ? 12 12 t cyc s sample/hold capacitance input capacitance on pd0/an0?pd7/an7 ? 12 pf input leakage (3) (3) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input cu rrent to a/d channel w ill be dependent on external source impedance (see figure 8-2 ). input leakage on a/d pins pd0/an0?pd7/an7, vrl, vrh ? 1 a
freescale f-24 mc68HC05B6 rev. 4.1 mc68hc705b16n 14 table f-10 a/d characteristics for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 ? bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) ? 1lsb quantization error uncertainty due to converter resolution ? 1lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors ? 2lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss ? 0.1 v rh v ? v r minimum difference between v rh and v rl 3?v conversion time total time to perfor m a single analog to digital conversion internal rc oscillator ? 32 s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conv ersion result when v in = v rl 00 ? hex full scale reading conversion result when v in = v rh ?ffhex sample acquisition time analog input acquisition sampling internal rc oscillator (1) ?12 s sample/hold capacitance input capacitance on pd0/an0?pd7/an7 ? 12 pf input leakage (2) input leakage on a/d pins pd0/an0?pd7/an7, vrl, vrh ? 1 a (1) source impedances greater than 10k ? will adversely affect internal charging time during input sampling. (2) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input current to a/d channel will be dependent on external source impedance (see figure 8-2 ).
mc68HC05B6 rev. 4.1 freescale f-25 mc68hc705b16n 14 f.9 control timing table f-11 control timing for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc ? dc 4.2 4.2 mhz mhz internal operating frequency (f osc /2) using crystal using external clock f op f op dc dc 2.1 2.1 mhz mhz cycle time (see figure 9-1 )t cyc 480 ? ns crystal oscillator start-up time (see figure 9-1 )t oxov ? 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms rc oscillator stabilization time t adrc 5 s a/d converter stabilization time t adon 500 s external reset input pulse width t rl 3.0 ? t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 ? ? t cyc t cyc watchdog reset output pulse width t dogl 1.5 ? t cyc watchdog time-out t dog 6144 7168 t cyc eeprom byte erase time 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 105 (industrial) ? 40 to 125 (automotive) t era t era t era t era 10 10 10 10 ? ? ? ? ms ms ms ms eeprom byte program time (1) 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 105 (industrial) ? 40 to 125 (automotive) (1) for bus frequencies less than 2 mhz, the internal rc oscillator should be used when programming the eeprom. t prog t prog t prog t prog 10 10 15 20 ? ? ? ? ms ms ms ms timer (see figure f-10 ) resolution (2) input capture pulse width input capture pulse period (2) since a 2-bit prescaler in the time r must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. t resl t th , t tl t tltl 4 125 ? (3) (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . ? ? ? t cyc ns t cyc interrupt pulse width (edge-triggered) t ilih 125 ? ns interrupt pulse period t ilil ? (4) (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . ?t cyc osc1 pulse width (5) (5) t oh and t ol should not total less than 238ns. t oh , t ol 90 ? ns write/erase endurance (6) (6) at a temperature of 85 c ? 10000 cycles data retention (6)(7) (7) refer to reliability monitor report (current quar terly issue) for current failure rate information. ? 10 years
freescale f-26 mc68HC05B6 rev. 4.1 mc68hc705b16n 14 table f-12 control timing for 3.3v operation (v dd = 3.3vdc 10%, v ss = 0 vdc, t a = t l to t h ) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc ? dc 2.0 2.0 mhz mhz internal operating frequency (f osc /2) using crystal using external clock f op f op ? dc 1.0 1.0 mhz mhz cycle time (see figure 9-1 )t cyc 1000 ? ns crystal oscillator start-up time (see figure 9-1 )t oxov ? 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms rc oscillator stabilization time t adrc 5 s a/d converter stabilization time t adon 500 s external reset input pulse width t rl 3.0 ? t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 ? ? t cyc t cyc watchdog reset output pulse width t dogl 1.5 ? t cyc watchdog time-out t dog 6144 7168 t cyc eeprom byte erase time 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 105 (industrial) ? 40 to 125 (automotive) t era t era t era t era 30 30 30 30 ? ? ? ? ms ms ms ms eeprom byte program time (1) 0 to 70 (standard) ? 40 to 85 (extended) ? 40 to 105 (industrial) ? 40 to 125 (automotive) t prog t prog t prog t prog 30 30 30 30 ? ? ? ? ms ms ms ms timer (see figure f-10 ) resolution (2) input capture pulse width input capture pulse period t resl t th , t tl t tltl 4 250 ? (3) ? ? ? t cyc ns t cyc interrupt pulse width (edge-triggered) t ilih 250 ? ns interrupt pulse period t ilil ? (4) ?t cyc osc1 pulse width (5) t oh , t ol 200 ? ns write/erase endurance (6)(7) ? 10000 cycles data retention (6)(7) ?10years (1) for bus frequencies less than 2 mhz, the internal rc oscillator should be used when programming the eeprom. (2) since a 2-bit prescaler in the time r must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . (5) t oh and t ol should not total less than 500ns. (6) at a temperature of 85 c (7) refer to reliability monitor report (current qua rterly issue) for current failure rate information.
mc68HC05B6 rev. 4.1 freescale f-27 mc68hc705b16n 14 f.10 eprom electrical characteristics figure f-10 timer relationship table f-13 dc electrical characteristics for 5v operation (v dd = 5 vdc 10%, v ss = 0 vdc, t a = 25 c) characteristic (1) (1) all i dd measurements taken with suitable decoupling capa citors across the power supply to suppress the transient switching currents inherent in cmos designs (see section 2). symbol min typ (2) (2) typical values are at mid point of voltage range and at 25 c only. max unit eprom absolute maximum voltage programming voltage programming current read voltage v pp6 max v pp6 i pp6 v pp6r v dd 15 ? v dd ? 15.5 50 v dd 18 16 64 v dd v v ma v table f-14 control timing for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = 25 c) characteristic symbol min max unit eprom programming time t prog 520ms table f-15 control timing for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = 25 c) characteristic symbol min max unit eprom programming time t prog 520ms external signal (tcap1, tcap2) t tltl t th t tl
freescale f-28 mc68HC05B6 rev. 4.1 mc68hc705b16n 14
mc68HC05B6 rev. 4.1 freescale g-1 mc68hc05b32 14 g mc68hc05b32 the mc68hc05b32 is a device similar to the mc68HC05B6, but with increased ram and rom sizes. the entire mc68HC05B6 data sheet applie s to the mc68hc05b32, with the exceptions outlined in this appendix. g.1 features 31248 bytes user rom no page zero rom 528 bytes of ram 52-pin plcc and 64-pin qfp packages for -40 to +85 c operating temperature range (extended) 56-pin sdip package for 0 to 70 c operating temperature range high speed version not available note: preliminary electrical specifications fo r the mc68hc05b32 should be taken as being similar to those for the mc68hc705b32. when silicon is fully available, the part will be re-characterised and new data made available. g.2 external clock when using an external clock the osc1 and os c2 pins should be driven in antiphase (see figure d-2 ). the t oxov or t ilch specifications (see section h.9 ) do not apply when using an external clock input. the equivalent specification of the external clock source should be used in lieu of t oxov or t ilch . 239 240 241 242
freescale g-2 mc68HC05B6 rev. 4.1 mc68hc05b32 14 figure g-1 mc68hc05b32 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp1 256 bytes eeprom charge pump 2 / 32 plma d/a plmb d/a 8-bit 32 kbytes rom 528 bytes static ram 638 bytes vpp6 self-check rom
mc68HC05B6 rev. 4.1 freescale g-3 mc68hc05b32 14 figure g-2 memory map of the mc68hc05b32 port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $7ff0 stack rami (176 bytes) $0250 $0200 $0050 port a data direction register port b data direction register port c data direction register eeprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f user rom (31232 bytes) bootloader romiii (478 bytes) $03b0 $7fe0 options register unprotected (31 bytes) protected (224 bytes) eeprom (256 bytes) $0101 $0120 $0100 options register reserved mc68hc05b32 registers ramii (352 bytes) $0400 bootloader romi (80 bytes) bootloader rom vectors (16 bytes) bootloader romii (80 bytes) $7e00 $7fde user vectors (14 bytes) $7ff2?3 sci timer overflow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $7ff4?5 $7ff6?7 $7ff8?9 $7ffa?b $7ffc?d $7ffe?f
freescale g-4 mc68HC05B6 rev. 4.1 mc68hc05b32 14 table g-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 undefined port b data (portb) $0001 undefined port c data (portc) $0002 pc2/ eclk undefined port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 undefined port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eeprom/eclk control $0007 0 0 0 0 eclk e1era e1lat e1pgm 0000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl undefined sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 undefined input capture high 1 $0014 undefined input capture low 1 $0015 undefined output compare high 1 $0016 undefined output compare low 1 $0017 undefined timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c undefined input capture low 2 $001d undefined output compare high 2 $001e undefined output compare low 2 $001f undefined options (optr) (3) $0100 ee1p sec not affected mask option register (mor) (4) $7fde rtim rwat wwat pbpd pcpd not affected (1) this bit is set each time there is a power-on reset. (2) the state of the wdog bit after rese t is dependent upon the mask option selected; 1 = watchdog enabled, 0 = watchdog disable d. (3) this register is implemented in eeprom; ther efore reset has no effect on the individual bits. (4) this register is implemented in rom; theref ore reset has no effect on the individual bits.
mc68HC05B6 rev. 4.1 freescale h-1 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y h mc68hc705b32 maskset errata this errata section outlines the differences between two previously available masksets (d59j and d40j) and all other masksets. unless otherwi se stated, the main body of appendix g refers to all these other masksets with any differences being noted in this errata section. for the d59j and d40j masksets, the mc u only requires that a logic zero is applied to the reset input for 1.5 t cyc . for d59j, 16 cycle por delay option (t porl ) is not available for the d59j maskset, oscilla tor divide ratio div10 is forced in bootstrap mode. on all other revisions div2 is forced. for the d59j: the stop idd is greater than the expected value of 120 a at 5 volts vdd at a temperature of 20 c with the can module enabled and in sl eep mode. typically the stop idd is in the region of 2.0 milliamps at 20 c. the fault lies with the design of the eprom array. when the stop instruction is executed, the next opcode in memory is present on the data bus. a fault in the eprom write data latch circuitry causes a latch to be driven to logic 0 on both sides when the data bus for that bit is logic 1. this results in increasing stop idd of 450 a per data bus bit set to a logic 1. if all data bus bits are set to logic 1 (i.e. next opcode is $ff, stx 0,x) the stop idd shall be in the region of 3.6ma. the minimum stop idd is achieved by ensuring the opcode immediately following the stop instruction is data $00. this co rresponds to brset 0,address,label. if the label points to the next sequential instructio n in memory then this has the effect of a 5 cycle nop but note that the carry bit in th e condition code register may be altered by the brset instruction. 243 244 245 246 247
freescale h-2 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y example stop brset 0,$00,next next any cpu instruction the address compared may be any address in the page zero memory and the only restriction is that it should not be a regist er with flags cleared by reading the register. the example shows the address compared to be port a data register and this should not cause any problems in any applications. high stop idd will be variable dependant upon the opcode following the stop instruction. the more bits set in the foll owing opcode, the higher the stop idd. the work around described above may be used on any 68hc05b32 or corrected version of the 68hc705b32 without problem. it simply adds a 5 cycle delay to the recovery from stop and 3 bytes of additional code per stop instruction but may alter the state of the carry bit in the ccr. also for the d59j: the eeprom programming circuit only fully supports 16-byte simultaneous programming mode and does not support single byte programming correctly. the fault lies with the design of the eprom ar ray. a fault in the eprom write data latch circuitry causes a latch to be driven to logic 0 on both sides when the data bus for that bit is logic 1. when the elat signal is re moved, there is a race condition with the epbs signal which results in the data bus value being copied to all the eprom latches. since 16-byte simultaneous programming functions correctly, it is a relatively simple matter to emulate single byte programming by first initialising all 16 data latches to $00 and then writing the data to be written to the appropriate address. this problem does not affect user applicatio n software in normally circumstances since it only applies to programming the eprom array. the serial programming software should always simulate 16-byte programming. the freescale software for programming the 705b32 from an ibm compatible pc functions in 16 byte programming mode. this program therefore correctly programs the eprom. in normal circumstances this errata does not affect the user application software. this only affects software that programs th e eprom array. the parallel programming bootloader software within the 705b32 rom performs 16-byte programming and so functions correctly. 248 249 250 251 252
mc68HC05B6 rev. 4.1 freescale h-3 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y the mc68hc705b32 is an eprom version of the mc68hc05b32, with the rom replaced by a similar amount of eprom. the entire mc68hc0 5b6 data sheet applies to the mc68hc705b32, with the exceptions outlined in this appendix. h.1 features 31246 bytes user eprom no page zero eprom at $20?$4f 528 bytes of ram 638 bytes bootstrap rom instead of 432 bytes of self-check rom simultaneous programming of eprom with up to 16 bytes of different data -40 to +85 c operating temperature range (extended) 52-pin plcc, 56-pin sdip and 64-pin qfp packages high speed version not available note: the electrical characteristics from the mc 68HC05B6 data sheet should not be used for the mc68hc705b32. data specific to this device can be found in section h.7 and section h.9 . 253 254 255 256 257
freescale h-4 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y figure h-1 mc68hc705b32 block diagram port a pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port b pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 port c pc0 pc1 pc2/eclk pc3 pc4 pc5 pc6 pc7 16-bit timer port d pd0/an0 pd1/an1 pd2/an2 pd3/an3 pd4/an4 pd5/an5 pd6/an6 pd7/an7 oscillator cop watchdog reset irq vdd vss osc1 osc2 m68hc05 cpu sci a/d converter plm tcap1 tcap2 tcmp1 tcmp2 vrh vrl rdi sclk tdo vpp1 256 bytes eeprom charge pump 2 / 32 plma d/a plmb d/a 8-bit 32 kbytes eprom 528 bytes static ram 638 bytes vpp6 bootstrap rom 258 259 260 261 262
mc68HC05B6 rev. 4.1 freescale h-5 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y figure h-2 memory map of the mc68hc705b32 bootstrap rom vectors (16 bytes) port b data register port c data register port d input data register port a data register $0000 compare low register 2 a/d data register $0000 i/o (32 bytes) $0020 $00c0 $0100 $7fde $7ff0?1 stack ram1 (176 bytes) $0250 $0200 $0050 port a data direction register port b data direction register port c data direction register e/eeprom/eclk control register a/d status/control register pulse length modulation a pulse length modulation b miscellaneous register sci baud rate register sci control register 1 sci control register 2 sci status register sci data register timer control register timer status register capture high register 1 capture low register 1 compare high register 1 compare low register 1 counter high register counter low register alternate counter high register alternate counter low register capture high register 2 capture low register 2 compare high register 2 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001a $001b $001c $001d $001e $001f bootstrap romii (80 bytes) $03b0 $7fe0 options register unprotected (31 bytes) protected (224 bytes) eeprom (256 bytes) $0101 $0120 $0100 options register reserved mc68hc705b32 registers ram11 (352 bytes) $0400 mask option register mask option register $7fde bootstrap romi (80 bytes) user eprom (31232 bytes) bootstrap romiii (478 bytes) $7e00 user vectors (14 bytes) $7ff2?3 sci timer overflow timer output compare 1& 2 timer input capture 1 & 2 external irq swi reset/power-on reset $7fdf $7ff4?5 $7ff6?7 $7ff8?9 $7ffa?b $7ffc?d $7ffe?f 263 264 265 266 267
freescale h-6 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y table h-1 register outline register name address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset port a data (porta) $0000 undefined port b data (portb) $0001 undefined port c data (portc) $0002 pc2/ eclk undefined port d data (portd) $0003 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 undefined port a data direction (ddra) $0004 0000 0000 port b data direction (ddrb) $0005 0000 0000 port c data direction (ddrc) $0006 0000 0000 eprom/eeprom/eclk control $0007 0 e6lat e6pgm eclk e1era e1lat e1pgm u000 0000 a/d data (addata) $0008 0000 0000 a/d status/control (adstat) $0009 coco adrc adon 0 ch3 ch2 ch1 ch0 0000 0000 pulse length modulation a (plma) $000a 0000 0000 pulse length modulation b (plmb) $000b 0000 0000 miscellaneous $000c por (1) intp intn inte sfa sfb sm wdog (2) ?001 000? sci baud rate (baud) $000d spc1 spc0 sct1 sct0 sct0 scr2 scr1 scr0 00uu uuuu sci control 1 (sccr1) $000e r8 t8 m wake cpol cpha lbcl undefined sci control 2 (sccr2) $000f tie tcie rie ilie te re rwu sbk 0000 0000 sci status (scsr) $0010 tdre tc rdrf idle or nf fe 1100 000u sci data (scdr) $0011 0000 0000 timer control (tcr) $0012 icie ocie toie folv2 folv1 olv2 iedg1 olvl1 0000 00u0 timer status (tsr) $0013 icf1 ocf1 tof icf2 ocf2 undefined input capture high 1 $0014 undefined input capture low 1 $0015 undefined output compare high 1 $0016 undefined output compare low 1 $0017 undefined timer counter high $0018 1111 1111 timer counter low $0019 1111 1100 alternate counter high $001a 1111 1111 alternate counter low $001b 1111 1100 input capture high 2 $001c undefined input capture low 2 $001d undefined output compare high 2 $001e undefined output compare low 2 $001f undefined options (optr) (3) $0100 ee1p sec not affected mask option register (mor) (4) $7fde rtim rwat wwat pbpd pcpd not affected (1) this bit is set each time there is a power-on reset. (2) the state of the wdog bit after reset is dependent upon t he mask option selected; 1=watchdog enabled, 0=watchdog disabled. (3) this register is implemented in eeprom; theref ore reset has no effect on the individual bits. (4) this register is implemented in eprom; theref ore reset has no effect on the individual bits. 268 269 270
mc68HC05B6 rev. 4.1 freescale h-7 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y h.2 external clock when using an external clock the osc1 and os c2 pins should be driven in antiphase (see figure d-2 ). the t oxov or t ilch specifications (see section h.9 ) do not apply when using an external clock input. the equivalent specification of the external clock source should be used in lieu of t oxov or t ilch . h.3 reset pin when the oscillator is running in a stable condition, the mcu is reset when a logic zero is applied to the reset input for a minimum period of 3.0 machine cycles (t cyc ). this differs from the 05b6, 05b4, 705b5, 05b8, 05b16, 705b16 and the 05b32, which require 1.5 t cyc . for more information see section 9.1.3 . h.4 eprom the mc68hc705b32 memory map is given in figure h-2 . the device has a total of 31246 bytes of eprom. 14 bytes are used for the reset and interrupt vectors from address $7ff2 to $7fff. the main eprom block of 31232 bytes is located from $0400 to $7dff. one byte of eprom is used as an options register and is located at address $7fde. the eprom array is supplied by the vpp6 pin in both read and program modes. typically the user?s software will be loaded into a programming board where v pp6 is controlled by one of the bootstrap loader routines. it will then be placed in an application where no programming occurs. in this case the vpp6 pi n should be hardwired to v dd . warning: a minimum v dd voltage must be applied to the vpp6 pin at all times, including power-on. failure to do so could result in permanent damage to the device. unless otherwise stated, eprom programmi ng is guaranteed at ambient (25 c) temperature only.
freescale h-8 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y h.4.1 eprom read operation the execution of a program in the eprom address range or a load from the eprom are both read operations. the e6lat bit in the eprom/eeprom control register should be cleared to ?0? which automatically resets the e6pgm bit. in this way the eprom is read like a normal rom. reading the eprom with the e6lat bit set will give data that does not correspond to the actual memory content. as interrupt vectors are in eprom, they will not be loaded when e6lat is set. similarly, the bootstrap rom rout ines cannot be executed when e6lat is set. in read mode, the vpp6 pin must be at the v dd level. when entering the stop mode, the eprom is automatically set to the read mode. note: an erased byte reads as $00. h.4.2 eprom program operation typically, the eprom will be programmed by the bo otstrap routines resident in the on-chip rom. however, the user program can be used to program some eprom locations if the proper procedure is followed. in particular, the programming sequence must be running in ram, as the eprom will not be available for code execution while the e6lat bit is set. the v pp6 switching must occur externally after epgm is set, for exampl e under control of a signal generated on a pin by the programming routine. note: unless the part has a window for reprogramming, only the cumulative programming of bits to logic ?1? is possible if multiple programming is made on the same byte. to allow simultaneous programming of up to sixteen bytes, these bytes must be in the same group of addresses which share the same most signific ant address bits; only the four lsbs can change. h.4.3 eprom/eeprom control register address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset eprom/eeprom/eclk control $0007 0 e6lat e6pgm eclk e1era e1lat e1pgm u000 0000
mc68HC05B6 rev. 4.1 freescale h-9 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y e6lat ? eprom programming latch enable bit 1 (set) ? address and up to sixteen data bytes can be latched into the eprom for further programming providing the e6pgm bit is cleared. when programming the eprom, all other 15 addresses must be latched with the erased state ($00) or corruption may occur. 0 (clear) ? data can be read from the epr om or firmware rom; the e6pgm bit is reset to zero when e6lat is ?0?. stop, power-on and external reset clear the e6lat bit. note: after the t era1 erase time or t prog1 programming time, the e6lat bit has to be reset to zero in order to clear the e6pgm bit. e6pgm ? eprom program enable bit this bit is the eprom program enable bit. it can be set to ?1? to enable programming only after e6lat is set and at least one byte is written to th e eprom. it is not possible to clear this bit using software but clearing e6lat will always clear e6pgm. note: all combinations are not shown in the above table, since the e6pgm bit is cleared when the e6lat bit is at zero, and will result in a read condition. eclk see section 4.3 . e1era ? eeprom erase/programming bit providing the e1lat and e1pgm bits are at logic one, this bit indicates whether the access to the eeprom is for erasing or programming purposes. 1 (set) ? an erase operation will take place. 0 (clear) ? a programming operation will take place. once the program/erase eeprom address has been selected, e1era cannot be changed. table h-2 eprom control bits description e6lat e6pgm description 0 0 read/execute in eprom 1 0 ready to write address/data to eprom 1 1 programming in progress
freescale h-10 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y e1lat ? eeprom programming latch enable bit 1 (set) ? address and data can be latched into the eeprom for further program or erase operations, prov iding the e1pgm bit is cleared. 0 (clear) ? data can be read from the eeprom. the e1era bit and the e1pgm bit are reset to zero when e1lat is ?0?. stop, power-on and external reset clear the e1lat bit. note: after the t era1 erase time or t prog1 programming time, the e1lat bit has to be reset to zero in order to clear the e1era bit and the e1pgm bit. e1pgm ? eeprom charge pump enable/disable 1 (set) ? internal charge pump generator switched on. 0 (clear) ? internal charge pump generator switched off. when the charge pump generator is on, the resulting hi gh voltage is applied to the eeprom array. this bit cannot be set before the data is selected, and once this bit has been set it can only be cleared by clearing the e1lat bit. a summary of the effects of settin g/clearing bits 0, 1 and 2 of the control register are given in ta b l e h - 3 . note: the e1pgm and e1era bits are cleared when the e1lat bit is at zero. table h-3 eeprom control bits description e1era e1lat e1pgm description 0 0 0 read condition 0 1 0 ready to load address/data for program/erase 0 1 1 byte programming in progress 1 1 0 ready for byte erase (load address) 1 1 1 byte erase in progress
mc68HC05B6 rev. 4.1 freescale h-11 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y h.4.4 mask option register rtim this bit can modify the time t porl , where the reset pin is kept low after a power-on reset. 1 (set) ? t porl = 16 cycles. 0 (clear) ? t porl = 4064 cycles. rwat this bit can modify the status of the watchdog counter after reset. usually, the watchdog system is disabled after power-on or external reset but wh en this bit is set, it will be active immediately after the following resets (except in bootstrap mode). wwat this bit can modify the status of the watchdog counter in wait mode. normally, the watchdog system is disabled in wait mode but when this bi t is set, the watchdog will be active in wait mode. pbpd this bit, when programmed, connects a resistive pull- down on all 8 pins of port b. this pull-down, r pd , is active on a given pin only while it is an input. pcpd this bit, when programmed, connects a resistive pull- down on all 8 pins of port c. this pull-down, r pd , is active on a given pin only while it is an input. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset mask option register (mor) (1) (1) because this register is implemented in eprom , reset has no effect on the individual bits. $7fde rtim rwat wwat pbpd pcpd not affected
freescale h-12 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y h.4.5 options register (optr) ee1p ? eeprom protect bit in order to achieve a higher deg ree of protection, the eeprom is effectively split into two parts, both working from the vpp1 charge pump. part 1 of the eeprom array (32 bytes from $0100 to $011f) cannot be protected; part 2 (224 bytes from $0120 to $01ff) is pr otected by the ee1p bit of the options register. 1 (set) ? part 2 of the eeprom array is not protected; all 256 bytes of eeprom can be accessed for any read, erase or programming operations. 0 (clear) ? part 2 of the eeprom array is protected; any attempt to erase or program a location will be unsuccessful. when this bit is set to 1 (erased), the protection will remain until the next power-on or external reset. ee1p can only be written to ?0? when the e1lat bit in the eeprom control register is set. note: the eeprom1 protect function is disa bled while in bootstrap mode. sec ? secure bit this bit allows the eprom and eeprom1 to be secured from external access. when this bit is in the erased state (set), the eprom and eeprom 1 content is not secured and the device may be used in non user mode. when the sec bit is programmed to ?zero?, the eprom and eeprom1 content is secured by prohibiting entry to the non user mode. to deactivate the secure bit, the eprom has to be erased by exposure to a high density ultraviolet light, and the device has to be entered into the eprom erase verification mode wi th pd1 set. when the sec bit is changed, its new value will have no effect until the next power-on or external reset. 1 (set) ? eeprom/eprom not protected. 0 (clear) ? eeprom/eprom protected. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on reset options (optr) (1) (1) because this register is implemented in ee prom, reset has no effect on the individual bits. $0100 ee1p sec not affected
mc68HC05B6 rev. 4.1 freescale h-13 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y h.5 bootstrap mode oscillator divide-by-two is forced in bootstrap mode. the 432 bytes of self-check firmware on the mc 68HC05B6 are replaced by 654 bytes of bootstrap firmware. a detailed description of the modes of operation within bootstrap mode is given below. the bootstrap program in mask rom address locations $0200 to $024f, $03b0 to $3fff, $7e00 to $7fdd and $7fe0 to $7fef can be used to program the eprom and the eeprom, to check if the eprom is erased or to load and execute data in ram. after reset, while going to the bootstrap mode, the vector located at address $7fee and $7fef (reset ) is fetched to start execution of the bootst rap program. to place the part in bootstrap mode, the irq pin should be at 2xv dd with the tcap1 pin ?high? during transition of the reset pin from low to high. the hold time on the irq and tcap1 pins is two clock cycles after the external reset pin is brought high. when the mc68hc705b32 is placed in the bootstrap mode, the bootstrap reset vector will be fetched and the bootstrap firmware will start to execute. ta b l e h - 4 shows the conditions required to enter each level of bootstrap mode on the rising edge of reset . the bootstrap program will first copy part of itse lf in ram (except ?ram parallel load?), as the program cannot be executed in rom during verification/programming of the eprom. it will then set the tcmp1 output to a logic high level, unlike the mc68HC05B6 which keeps tcmp1 low. this can be used to distinguish between the two circuits and, in particular, for selection of the vpp level and current capability. table h-4 mode of operation selection irq pin tcap1 pin pd1 pd2 pd3 pd4 mode v ss to v dd v ss to v dd xxxxsingle chip 2xv dd v dd 0 0 0 x erased eprom verification 2xv dd v dd 1000 eprom verification; erase eeprom; eprom/eeprom parallel program/verify 2xv dd v dd 0100 erased eprom verification; no eeprom erase if sec is zero (parallel mode) 2xv dd v dd 1100 erased eprom verification; erase eeprom; eprom parallel program/verify (no e 2 ) 2xv dd v dd x 1 1 0 jump to start of ram ($0051); sec bit = active 2xv dd v dd 0101eprom and eeprom verification; sec bit = active (parallel mode) 2xv dd v dd xx11 serial ram load/execute ? similar to mc68HC05B6 but can fill ram i, ii and iii x = don?t care
freescale h-14 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y figure h-3 modes of operation flow chart (1 of 2) red led on tcap1=v dd ? sec bit active? pd3 set? reset user mode red led on non-user mode non-user mode n y y y y n y n n bootstrap mode parallel e/eeprom bootstrap n pd4 set? y erased eprom verification serial ram load/execute n pd2 set? y n jump to ram ($0051) pd2 set? n pd1 set? y n sec bit active? red led on y n pd4 set? y eprom erased? n y y green led on pd1 set? n erase eeprom1 red led off n a b c sec bit active? irq at 2xv dd ?
mc68HC05B6 rev. 4.1 freescale h-15 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y figure h-4 modes of operation flow chart (2 of 2) data verified? y pd2 set? n n red led on a base address = $400 (eprom only) base address = $100 (eprom and eeprom) y n green led on b c pd2 set? n y base address = $400 (eprom only) base address = $400 (eprom only)
freescale h-16 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y h.5.1 erased eprom verification if a non $00 byte is detected, the red led wi ll be turned on and the routine will stop (see figure h-3 and figure h-4 ). only when the whole eprom content is verified as erased will the green led be turned on. pd1 is then checked. if pd1=0, the bootstrap program stops here and no programming occurs until such time as a high le vel is sensed on pd1. if pd1 = 1, the bootstrap program proceeds to erase the eeprom1 for a nominal 2.5 seconds (4.0 mhz crystal). it is then checked for complete erasure; if any eeprom byte is not erased, the program will stop before erasing the sec byte. when both eprom and eepr om1 are completely erased and the security bit is cleared the programming operation can be performed. a schematic diagram of the circuit required for erased eprom verification is shown in figure h-7 . h.5.2 eprom/eeprom parallel bootstrap within this mode there are various subsections which can be utilised by correctly configuring the port pins shown in ta bl e h - 4 . the erased eprom verification program will be executed first as described in section h.5.1 . when pd2=0, the programming time is set to 5 milliseconds with the bootstrap program and verify for the eprom taking approximately 15 seconds. the eprom will be loaded in increasing address order with non eprom segments being skipped by the loader. simultaneous programming is performed by reading sixteen bytes of data before actual programming is performed, thus dividing the loading time of the internal eprom by 16. if any block of 16 eprom bytes or 1 eeprom byte of data is in the eras ed state, no programming takes place, thus speeding up the execution time. parallel data is entered through port a, while the 15 -bit address is output on port b, pc0 to pc4 and tcmp1 and tcmp2. if the data comes from an external eprom, the handshake can be disabled by connecting together pc5 and pc6. if the data is supplied by a parallel interface, handshake will be provided by pc5 and pc6 according to the timing diagram of figure h-5 (see also figure h-6 ). during programming, the green led will flash at about 3 hz. upon completion of the programming operati on, the eprom and eepr om1 content will be checked against the external data source. if pr ogramming is verified the green led will stay on, while an error will cause the red led to be turned on. figure h-7 is a schematic diagram of a circuit which can be used to program the eprom or to load and execute data in the ram. note: the entire eprom and eeprom1 can be loaded from the external source; if it is desired to leave a segment undisturbed, the data for this segment should be all $00s for eprom data and all $ffs for eeprom1 data.
mc68HC05B6 rev. 4.1 freescale h-17 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y figure h-5 timing diagram with handshake figure h-6 parallel eprom loader timing diagram data read data read address hdsk out (pc5) data hdsk in (pc6) f29 t cooe t ade t dhe address data t ade t dhe t ade t dhe t ade t dhe t cooe t cooe t cdde t ade max (address to data delay) 5 machine cycles t dha min (data hold time) 14 machine cycles t cooe (load cycle time) 117 machine cycles < t cooe < 150 machine cycles t cdde (programming cycle time) t cooe + t prog (5ms nominal for eprom; 10ms for eeprom1)) 1 machine cycle = 1/(2f 0 (xtal))
freescale h-18 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y figure h-7 eprom parallel bootstrap schematic diagram vcc 28 1 vpp pgm 27 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 vdd osc1 osc2 tcap1 irq reset vss a0 a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 gnd oe 14 22 10 9 8 7 6 5 4 26 12 13 15 16 17 18 19 11 3 +5v 1 2 p1 gnd +5v 100 f 22pf 4.0 mhz 1n914 1k ? 1.0 f 22pf 100k ? 1n914 reset run 0.01 f tdo sclk rdi vrl tcap2 pd7 pd6 pd5 pd3 pd2 pd1 pd0 pd4 +5v 3 v pp vpp6 pc7 pc5 pc4 pc3 pc2 pc1 pc0 pc6 24 21 23 2 a9 a8 a10 a12 ce a11 a12 a11 a10 a9 a8 hdsk out hdsk in short circuit if handshake not used 100 k ? nc tcmp1 tcmp2 plma plmb 470 ? 470 ? red led green led 4k7 ? 4k7 ? 12 k ? bc239c bc309c 10k ? 27c256 + + vrh red led ? programming failed green led ? programming ok 25 1nf 1n5819 1 k ? + ram eprom green led ? eprom erased 47 f + erase check & boot eprom erase check vpp1 red led ? eprom not erased boot erase check a13 20 mc68hc705b32 mcu a14 verify program eprom eprom note: this circuit is recommended for programming only at 25 c and not for use in the end application, or at temperatures other than 25 c. if used in the end application, vpp6 should be tied to vdd to avoid damaging the device.
mc68HC05B6 rev. 4.1 freescale h-19 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y h.5.3 serial ram loader this mode is similar to the ram load/execute program for the mc68HC05B6 described in section 2.2 , with the additional features listed below. ta b l e h - 4 shows the entry conditions required for this mode. if the first byte is less than $b0, the bootloa der behaves exactly as the mc68HC05B6, i.e. count byte followed by data stored in $0050 to $00ff. if the count byte is larger than ram i (176 bytes) then the code continues to fill ram ii then ram iii. in this case the count byte is ignored and the program execution begins at $0051 once the total ram area is filled or if no data is received for 5 milliseconds. the user must take care when using branches or jumps as his code will be relocated in ram i, ii and iii. if the user intends to use the stack in his program, he should send nop?s to fill the desired stack area. in the ram bootloader mode, all interrupt ve ctors are mapped to pseudo-vectors in ram (see ta bl e h - 5 ). this allows programmers to use t heir own service-routine addresses. each pseudo-vector is allowed three bytes of spac e rather than the two bytes for normal vectors, because an explicit jump (jmp) opcode is nee ded to cause the desired jump to the users service-routine address. h.5.3.1 jump to st art of ram ($0051) the jump to start of ram program will be execut ed when bring the device out of reset with pd2 and pd3 at ?1? and pd4 at ?0?. table h-5 bootstrap vector targets in ram vector targets in ram sci interrupt $0063 timer overflow $0060 timer output compare $005d timer input capture $005a irq $0057 swi $0054
freescale h-20 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y figure h-8 ram load and execute schematic diagram green led ? programming ended flashing green led ? programming 40 vpp6 pc7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 pa 6 pa 7 vdd osc1 osc2 tcap1 irq reset vss 1 2 p1 gnd +5v 1n914 1k ? 1.0 f 100k ? 1n914 reset run 0.01 f 3 v pp pc5 pc4 pc3 pc2 pc1 pc0 pc6 plma plmb 470 ? 470 ? red led green led + + vrh 22 f 22 f 22 f 2 x 3k ? 1 2 3 4 8 6 7 5 11 12 13 14 15 16 5 3 2 1 22 f rs232 connector max 232 +5v 9600 bd 8-bit no parity 19 18 20 21 50 52 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 14 13 12 5 4 43 44 45 46 47 48 49 23 2 1 51 22 8 10 41 7 vrl tcap2 tcmp1 tcmp2 sclk nc 10nf 47 f pd0 pd4 pd1 pd2 pd5 pd6 pd7 + + + + 22pf 4.0 mhz 22pf 4k7 ? 4k7 ? 12 k ? bc239c bc309c 10k ? 1nf 1n5819 1 k ? + serial boot erase check 47 f + pd3 rdi tdo erase check red led ? eprom not erased green led ? eprom erased serial boot & serial boot erase check and serial boot eprom erase check vpp1 3 mc68hc705b32 mcu (socket) note: a minimum v dd voltage must be applied to the vpp6 pin at all times, including power-on, as a lower voltage could damage the device. unless otherwise stated, eprom programming is guaranteed at ambient (25 c) temperature only
mc68HC05B6 rev. 4.1 freescale h-21 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y figure h-9 parallel ram loader timing diagram t adr t dhr address data t cr pd4 t exr max t ho t hi max pc5 out pc6 in t adr max (address to data delay; pc6=pc5) 16 machine cycles t dhr min (data hold time) 4 machine cycles t cr (load cycle time; pc6=pc5) 49 machine cycles t ho (pc5 handshake out delay) 5 machine cycles t hi max (pc6 handshake in, data hold time) 10 machine cycles t exr max (max delay for transition to be recognise d during this cycle; pc6=pc5 30 machine cycles 1 machine cycle = 1/(2f 0 (xtal))
freescale h-22 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y h.6 absolute maximum ratings note: this device contains circuitry designed to protect against damage due to high electrostatic voltages or electric fields . however, it is recommended that normal precautions be taken to avoid the applicati on of any voltages higher than those given in the maximum ratings table to this high impedance circuit. for maximum reliability all unused inputs should be tied to either v ss or v dd . table h-6 absolute maximum ratings rating symbol value unit supply voltage (1) (1) all voltages are with respect to v ss . v dd ? 0.5 to +7.0 v input voltage (except v pp1 and v pp6 )v in v ss ? 0.5 to v dd + 0.5 v input voltage ? self-check mode (irq pin only) v in v ss ? 0.5 to 2v dd + 0.5 v operating temperature range ? standard (mc68hc705b32) ? extended (mc68hc705b32c) t a t l to t h 0 to +70 ?40 to +85 c storage temperature range t stg ? 65 to +150 c current drain per pin (excluding vdd and vss) (2) ? source ? sink (2) maximum current drain per pin is for one pin at a time, limited by an external resistor. i d i s 25 45 ma ma
mc68HC05B6 rev. 4.1 freescale h-23 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y h.7 dc electrical characteristics table h-7 dc electrical characteristics for 5v operation (v dd = 5 vdc 10%, v ss = 0 vdc, ?40 to +85 c) characteristic (1) (1) all i dd measurements taken with suitable decoupling capacitors ac ross the power supply to suppr ess the transient switching currents inherent in cmos designs (see section 2). symbol min typ (2) (2) typical values are at mid point of voltage range and at 25 c only. max unit output voltage i load = ? 10 a i load = +10 a v oh v ol v dd ? 0.1 ? ? ? ? 0.1 v output high voltage (i load = 0.8ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2 output high voltage (i load = 1.6ma) tdo, sclk, plma, plmb output high voltage (i load = -300 a) osc2 v oh v oh v oh v dd ? 0.8 v dd ? 0.8 v dd ? 0.8 v dd ? 0.4 v dd ? 0.4 v dd ? 0.3 ? ? ? v output low voltage (i load = 1.6ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 1.6ma) reset output low voltage (i load = -100 a) osc2 v ol v ol v ol ? ? ? 0.1 0.4 tbd 0.4 1 ? v input high voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset , tcap1, tcap2, rdi v ih 0.7v dd ?v dd v input low voltage pa0?7, pb0?7, pc0?7, pd0?7,osc1, irq , reset , tcap1, tcap2, rdi v il v ss ?0.2v dd v supply current (3) (for guidance only) run (sm = 0) (see figure 11-1 ) run (sm = 1) (see figure 11-2 ) wait (sm = 0) (see figure 11-3 ) wait (sm = 1) (see figure 11-4 ) stop 0 to 70 (standard) ? 40 to 85 (extended) i dd i dd i dd i dd i dd i dd ? ? ? ? ? ? 6 1.5 2 1 10 10 tbd tbd tbd tbd tbd tbd ma ma ma ma a a high-z leakage current pa0?7, pb0?7, pc0?7, tdo, reset , sclk i il ? 0.2 1 a input current port b and port c pull-down (v in =v ih )i rpd 80 a input current (0 to 70) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ? 0.2 1 a input current (? 40 to 85) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ?? 5 a capacitance ports (as input or output), reset , tdo, sclk irq , tcap1, tcap2, osc1, rdi pd0/an0?pd7/an7 (a/d off) pd0/an0?pd7/an7 (a/d on) c out c out c in c in ? ? ? ? ? ? 12 22 12 8 ? ? pf pf pf pf
freescale h-24 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y (3) run and wait i dd : measured using an external square-wave clock source (f osc = 2.0 mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all ports configured as inputs; v il = 0.2 v and v ih =v dd ? 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance.
mc68HC05B6 rev. 4.1 freescale h-25 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y table h-8 dc electrical characteristics for 3.3v operation (v dd = 3.3vdc 10%, v ss = 0vdc, t a = ?40 to +85 c) characteristic (1) (1) all i dd measurements taken with suitable decoupling capa citors across the power supply to suppress the transient switching currents inherent in cmos designs (see section 2). symbol min typ (2) (2) typical values are at mid point of voltage range and at 25 c only. max unit output voltage i load = ? 10 a i load = +10 a v oh v ol v dd ? 0.1 ? ? ? ? 0.1 v output high voltage (i load = 0.8ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2 output high voltage (i load = 1.6ma) tdo, sclk, plma, plmb v oh v oh v dd ? 0.3 v dd ? 0.3 v dd ? 0.1 v dd ? 0.1 ? ? v output low voltage (i load = 1.6ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 1.6ma) reset v ol v ol ?0.1 0.2 0.3 0.6 v input high voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset , tcap1, tcap2, rdi v ih 0.7v dd ?v dd v input low voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset , tcap1, tcap2, rdi v il v ss ?0.2v dd v supply current (3) (for guidance only) run (sm = 0) (see figure 11-1 ) run (sm = 1) (see figure 11-2 ) wait (sm = 0) (see figure 11-3 ) wait (sm = 1) (see figure 11-4 ) stop 0 to 70 (standard) ? 40 to 85 (extended) (3) run and wait i dd : measured using an external square-wave clock source (f osc = 2.0 mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all ports configured as inputs; v il = 0.2 v and v ih =v dd ? 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance. i dd i dd i dd i dd i dd i dd ? ? ? ? ? ? 3 1 1.5 0.5 10 10 tbd tbd tbd tbd tbd tbd ma ma ma ma a a high-z leakage current pa0?7, pb0?7, pc0?7, tdo, reset , sclk i il ? 0.2 1 a input current (0 to 70) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ? 0.2 1 a input current (? 40 to 125) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ?? 5 a capacitance ports (as input or output), reset , tdo, sclk irq , tcap1, tcap2, osc1, rdi pd0/an0?pd7/an7 (a/d off) pd0/an0?pd7/an7 (a/d on) c out c out c in c in ? ? ? ? ? ? 12 22 12 8 ? ? pf pf pf pf
freescale h-26 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y h.8 a/d converte r characteristics table h-9 a/d characteristics for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40 to +85 c) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 ? bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) ? 0.5 lsb quantization error uncertainty due to converter resolution ? 0.5 lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors ? 1lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss ? 0.1 v rh v ? v r minimum difference between v rh and v rl 3?v conversion time total time to perfor m a single analog to digital conversion a. external clock (osc1, osc2) b. internal rc oscillator ? ? 32 32 t cyc s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conv ersion result when v in = v rl 00 ? hex full scale reading conversion result when v in = v rh ?ffhex sample acquisition time analog input acquisition sampling a. external clock (osc1, osc2) b. internal rc oscillator (1) (1) source impedances greater than 10k ? will adversely affect internal charging time during input sampling. ? ? 12 12 t cyc s sample/hold capacitance input capacitance on pd0/an0?pd7/an7 ? 12 pf input leakage (2) (2) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input current to a/d channel will be dependent on external source impedance (see figure 8-2 ). input leakage on a/d pins pd0/an0?pd7/an7, vrl, vrh ? 1 a
mc68HC05B6 rev. 4.1 freescale h-27 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y table h-10 a/d characteristics for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = ?40 to +85 c) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 ? bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) ? 1lsb quantization error uncertainty due to converter resolution ? 1lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors ? 2lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss ? 0.1 v rh v ? v r minimum difference between v rh and v rl 3?v conversion time total time to perform a single analog to digital conversion internal rc oscillator ? 32 s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conversion result when v in = v rl 00 ? hex full scale reading conversion result when v in = v rh ?ffhex sample acquisition time analog input acquisition sampling internal rc oscillator (1) ?12 s sample/hold capacitance input capacitance on pd0/an0?pd7/an7 ? 12 pf input leakage (2) input leakage on a/d pins pd0/an0?pd7/an7, vrl, vrh ? 1 a (1) source impedances greater than 10k ? will adversely affect internal charging time during input sampling. (2) the external system error caused by input leakage current is approximately equal to the product of r source and input current. input cu rrent to a/d channel w ill be dependent on external source impedance (see figure 8-2 ).
freescale h-28 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y h.9 control timing table h-11 control timing for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40 to +85 c) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc ? dc 4.2 4.2 mhz mhz internal operating frequency (f osc /2) using crystal using external clock f op f op ? dc 2.1 2.1 mhz mhz cycle time (see figure 9-1 )t cyc 476 ? ns crystal oscillator start-up time (see figure 9-1 )t oxov ? 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms rc oscillator stabilization time t adrc 5 s a/d converter stabilization time t adon 500 s external reset input pulse width t rl 3.0 ? t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 ? ? t cyc t cyc watchdog reset output pulse width t dogl 1.5 ? t cyc watchdog time-out t dog 6144 7168 t cyc eeprom byte erase time 0 to 70 (standard) ? 40 to 85 (extended) t era t era 10 10 ? ? ms ms eeprom byte program time (1) 0 to 70 (standard) ? 40 to 85 (extended) (1) for bus frequencies less than 2 mhz, the in ternal rc oscillator should be used when programming the eeprom. t prog t prog 10 10 ? ? ms ms timer (see figure h-10 ) resolution (2) input capture pulse width input capture pulse period (2) since a 2-bit prescaler in the time r must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. t resl t th , t tl t tltl 4 125 ? (3) (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . ? ? ? t cyc ns t cyc interrupt pulse width (edge-triggered) t ilih 125 ? ns interrupt pulse period t ilil ? (4) (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . ?t cyc osc1 pulse width (5) (5) t oh and t ol should not total less than 238ns. t oh , t ol 90 ? ns write/erase endurance (6)(7) (6) at a temperature of 85 c ? 10000 cycles data retention (6)(7) (7) refer to reliability monitor report (current quar terly issue) for current failure rate information. ? 10 years
mc68HC05B6 rev. 4.1 freescale h-29 mc68hc705b32 14 p r e li m in a r y p r e li m i n a r y p r e l i m in a r y table h-12 control timing for operation at 3.3v (v dd = 3.3vdc 10%, v ss = 0 vdc, t a = ?40 to +85 c) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc ? dc 2.0 2.0 mhz mhz internal operating frequency (f osc /2) using crystal using external clock f op f op ? dc 1.0 1.0 mhz mhz cycle time (see figure 9-1 )t cyc 1000 ? ns crystal oscillator start-up time (see figure 9-1 )t oxov ? 100 ms stop recovery start-up time (crystal oscillator) t ilch 100 ms rc oscillator stabilization time t adrc 5 s a/d converter stabilization time t adon 500 s external reset input pulse width t rl 3.0 ? t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 ? ? t cyc t cyc watchdog reset output pulse width t dogl 1.5 ? t cyc watchdog time-out t dog 6144 7168 t cyc eeprom byte erase time 0 to 70 (standard) ? 40 to 85 (extended) t era t era 30 30 ? ? ms ms eeprom byte program time (1) 0 to 70 (standard) ? 40 to 85 (extended) t prog t prog 30 30 ? ? ms ms timer (see figure h-10 ) resolution (2) input capture pulse width input capture pulse period t resl t th , t tl t tltl 4 250 ? (3) ? ? ? t cyc ns t cyc interrupt pulse widt h (edge-triggered) t ilih 250 ? ns interrupt pulse period t ilil ? (4) ?t cyc osc1 pulse width (5) t oh , t ol 100 ? ns write/erase endurance (6)(7) ? 10000 cycles data retention (6)(7) ? 10 years (1) for bus frequencies less than 2 mhz, the in ternal rc oscillator should be used when programming the eeprom. (2) since a 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . (5) t oh and t ol should not total less than 500ns. (6) at a temperature of 85 c (7) refer to reliability monitor report (current quar terly issue) for current failure rate information.
freescale h-30 mc68HC05B6 rev. 4.1 mc68hc705b32 14 p r e lim in a r y p r e li m i n a r y p r e l im in a r y this page left bl ank intentionally h.10 eprom electrical characteristics figure h-10 timer relationship table h-13 dc electrical characteristics for 5v operation (v dd = 5 vdc 10%, v ss = 0 vdc, t a = 25 c) characteristic (1) (1) all i dd measurements taken with suitable decoupling capac itors across the power supply to suppress the transient switching currents inherent in cmos designs (see section 2). symbol min typ (2) (2) typical values are at mid point of voltage range and at 25 c only. max unit eprom absolute maximum voltage programming voltage programming current read voltage v pp6 max v pp6 i pp6 v pp6r v dd 15 ? v dd ? 15.5 50 v dd 18 16 64 v dd v v ma v table h-14 control timing for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = 25 c) characteristic symbol min max unit eprom programming time t prog 520ms table h-15 control timing for 3.3v operation (v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = 25 c) characteristic symbol min max unit eprom programming time t prog 520ms external signal (tcap1, tcap2) t tltl t th t tl
mc68HC05B6 rev. 4.1 freescale i-1 high speed operation 15 271 272 273 274 275 i high speed operation this section contains the electric al specifications and associated timing information for high speed versions of the mc68HC05B6, mc68hc05b8 and mc68hc05b16 (f osc max = 8 mhz). the ordering information for these devices is contained in ta b l e i - 1 . note: the high speed version has the same device title as the standard version. high speed operation is selected via a check-box on the order form and will be confirmed on the listing verification form. table i-1 ordering information device title package suffix 0 to 70 c suffix -40 to +85 c mc68HC05B6 52-pin plcc fn cfn 64-pin qfp fu cfu 56-pin sdip b cb mc68hc05b8 52-pin plcc fn cfn 64-pin qfp fu cfu 56-pin sdip b cb mc68hc05b16 52-pin plcc fn cfn 64-pin qfp fu cfu 56-pin sdip b cb
freescale i-2 mc68HC05B6 rev. 4.1 high speed operation 15 i.1 dc electrical characteristics table i-2 dc electrical characteristics for 5v operation (v dd = 5 vdc 10%, v ss = 0 vdc, t a = ?40 to +85 c) characteristic (1) (1) all i dd measurements taken with suitable decoupling capacitor s across the power supply to suppress the transient switching currents inherent in cmos designs (see section 2). symbol min typ (2) (2) typical values are at mid poi nt of voltage range and at 25 c only. max unit output voltage i load = ? 10 a i load = +10 a v oh v ol v dd ? 0.1 ? ? ? ? 0.1 v output high voltage (i load = 0.8ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2 output high voltage (i load = 1.6ma) tdo, sclk, plma, plmb v oh v oh v dd ? 0.8 v dd ? 0.8 ? ? ? ? ? v output low voltage (i load = 1.6ma) pa0?7, pb0?7, pc0?7, tcmp1, tcmp2, tdo, sclk, plma, plmb output low voltage (i load = 1.6ma) reset v ol v ol ? ? ? ? ? ? 0.4 1 v input high voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset , tcap1, tcap2, rdi v ih 0.7v dd ?v dd v input low voltage pa0?7, pb0?7, pc0?7, pd0?7, osc1, irq , reset , tcap1, tcap2, rdi v il v ss ?0.2v dd v supply current (3) run (sm = 0) (see figure 11-1 ) run (sm = 1) (see figure 11-2 ) wait (sm = 0) (see figure 11-3 ) wait (sm = 1) (see figure 11-4 ) stop 0 to 70 (standard) ? 40 to 85 (extended) (3) run and wait i dd : measured using an external square-wave clock source (f osc = 8.0mhz); all inputs 0.2 v from rail; no dc loads; maximum load on outputs 50pf (20pf on osc2). stop /wait i dd : all ports configured as inputs; v il = 0.2 v and v ih =v dd ? 0.2 v: stop i dd measured with osc1 = v dd . wait i dd is affected linearly by the osc2 capacitance. i dd ? ? ? ? ? ? ? ? ? ? ? ? 12 3 4 2 10 20 ma ma ma ma a a high-z leakage current pa0?7, pb0?7, pc0?7, tdo, reset , sclk i il ?? 1 a input current (0 to 70) irq , osc1, tcap1, tcap2, rdi, pd0/an0-pd7/an7 (channel not selected) i in ?? ? 5 1 a capacitance ports (as input or output), reset , tdo, sclk irq , tcap1, tcap2, osc1, rdi pd0/an0?pd7/an7 (a/d off) pd0/an0?pd7/an7 (a/d on) c out c in c in c in ? ? ? ? ? ? 12 22 12 8 ? ? pf pf pf pf 276
mc68HC05B6 rev. 4.1 freescale i-3 high speed operation 15 i.2 a/d converter characteristics table i-3 a/d characteristics for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40 to +85 c) characteristic parameter min max unit resolution number of bits resolved by the a/d 8 ? bit non-linearity max deviation from the best straight line through the a/d transfer characteristics (v rh = v dd and v rl = 0v) ? 0.5 lsb quantization error uncertainty due to converter resolution ? 0.5 lsb absolute accuracy difference between the actual input voltage and the full-scale equivalent of the binary code output code for all errors ? 1lsb conversion range analog input voltage range v rl v rh v v rh maximum analog reference voltage v rl v dd + 0.1 v v rl minimum analog reference voltage v ss ? 0.1 v rh v ? v r (1) (1) performance verified down to 2.5v ? vr, but accuracy is tested and guaranteed at ? vr = 5v 10%. minimum difference between v rh and v rl 3?v conversion time total time to perform a single analog to digital conversion a. external clock (osc1, osc2) b. internal rc oscillator ? ? 32 32 t cyc s monotonicity conversion result never decreases with an increase in input voltage and has no missing codes guaranteed zero input reading conversion result when v in = v rl 00 ? hex full scale reading conversion result when v in = v rh ?ffhex sample acquisition time analog input acquisition sampling a. external clock (osc1, osc2) b. internal rc oscillator (2) (2) source impedances greater than 10k ? will adversely affect internal c harging time during input sampling. ? ? 12 12 t cyc s sample/hold capacitance input capacitance on pd0/an0?pd7/an7 ? 12 pf input leakage (3) (3) the external system error caused by input leakag e current is approximately equal to the product of r source and input current. input current to a/d c hannel will be dependent on external source impedance (see figure 8-2 ). input leakage on a/d pins pd0/an0?pd7/an7 vrl, vrh ? ? 1 1 a a
freescale i-4 mc68HC05B6 rev. 4.1 high speed operation 15 i.3 control timing for 5v operation (v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = ?40 to +85 c) characteristic symbol min max unit frequency of operation crystal option external clock option f osc f osc ? dc 8.0 8.0 mhz mhz internal operating frequency (f osc /2) crystal external clock f op f op ? dc 4.0 4.0 mhz mhz cycle time (see figure 9-1 )t cyc 250 ? ns crystal oscillator start-up time (see figure 9-1 )t oxov ?100ms stop recovery start-up time (crystal oscillator) t ilch 100 ms external reset input pulse width t rl 1.5 ? t cyc power-on reset output pulse width 4064 cycle 16 cycle t porl t porl 4064 16 ? ? t cyc t cyc watchdog reset output pulse width t dogl 1.5 ? t cyc watchdog time-out t dog 6144 7168 t cyc eeprom byte erase time 0 to 70 (standard) ? 40 to 85 (extended) t era t era 10 10 ? ? ms ms eeprom byte program time (1) 0 to 70 (standard) ? 40 to 85 (extended) (1) for bus frequencies less than 2 mhz, the internal rc oscillator should be used when programming the eeprom. t prog t prog 10 10 ? ? ms ms timer (see figure i-1 ) resolution (2) input capture pulse width input capture pulse period (2) since a 2-bit prescaler in the timer must count four external cycles (t cyc ), this is the limiting factor in determining the timer resolution. t resl t th , t tl t tltl 4 125 ? (3) (3) the minimum period t tltl should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus 24 t cyc . ? ? ? t cyc ns t cyc interrupt pulse widt h (edge-triggered) t ilih 125 ? ns interrupt pulse period t ilil ? (4) (4) the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 t cyc . ?t cyc osc1 pulse width t oh , t ol 90 ? ns write/erase endurance (5)(6) (5) at a temperature of 85 c ? 10000 cycles data retention (5)(6) (6) refer to reliability monitor report (current quarterly issu e) for current failure rate information. ?10years
mc68HC05B6 rev. 4.1 freescale i-5 high speed operation 15 figure i-1 timer relationship external signal (tcap1, tcap2) t tltl t th t tl
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mc68HC05B6 freescale i glossary glossary this section contains abbreviations and specialist words used in this data sheet and throughout the industry. further information on many of the terms may be gleaned from freescale?s m68hc11 reference manual, m68hc11rm/ad , or from a variety of standard electronics text books. $xxxx the digits following the ?$? are in hexadecimal format. %xxxx the digits following the ?%? are in binary format. a/d , adc analog-to-digital (converter). bootstrap mode in this mode the device automatically loads its internal memory from an external source on reset and then allows this program to be executed. byte eight bits. ccr condition codes register; an integral part of the cpu. cerquad a ceramic package type, principally used for eprom and high temperature devices. clear ?0? ? the logic zero state; the opposite of ?set?. cmos complementary metal oxide semiconductor. a semiconductor technology chosen for its low power consumption and good noise immunity. cop computer operating properly. aka ?watchdog?. this circuit is used to detect device runaway and provide a means for restoring correct operation. cpu central processing unit. d/a, dac digital-to-analog (converter). eeprom electrically erasable programmable read only memory. aka ?eerom?. eprom erasable programmable read only memory. this type of memory requires exposure to ultra-violet wavelengths in order to erase previous data. aka ?prom?. esd electrostatic discharge. expanded mode in this mode the internal address an d data bus lines are connected to external pins. this enables the device to be used in much more complex systems, where there is a need for external memory for example. tpg 277
freescale ii mc68HC05B6 glossary evs evaluation system. one of t he range of platforms provided by freescale for evaluation and emulation of their devices. hcmos high-density complementary metal oxide semiconductor. a semiconductor technology chosen for its low power consumption and good noise immunity. i/o input/output; used to describe a bidirectional pin or function. input capture (ic) this is a function provided by the timing system, whereby an external event is ?captured? by storing the value of a counter at the instant the event is detected. interrupt this refers to an asynchronous external event and the handling of it by the mcu. the external event is detected by the mcu and causes a predetermined action to occur. irq interrupt request. the overline indicates that this is an active-low signal format. k byte a kilo-byte (of memory); 1024 bytes. lcd liquid crystal display. lsb least significant byte. m68hc05 freescale?s family of 8-bit mcus. mcu microcontroller unit. mi bus interconnect bus. a single wire, medium speed serial communications protocol. msb most significant byte. nibble half a byte; four bits. nrz non-return to zero. opcode the opcode is a byte which identifies th e particular instruction and operating mode to the cpu. see also: prebyte, operand. operand the operand is a byte containing in formation the cpu needs to execute a particular instruction. there may be fr om 0 to 3 operands associated with an opcode. see also: opcode, prebyte. output compare (oc) this is a function provided by the timing system, whereby an external event is generated when an internal counter value matches a predefined value. plcc plastic leaded chip carrier package. pll phase-locked loop circuit. this provides a method of frequency multiplication, to enable the use of a low frequency crystal in a high frequency circuit. prebyte this byte is sometimes required to qualify an opcode, in order to fully specify a particular instruction. see also: opcode, operand. tpg 278
mc68HC05B6 freescale iii glossary pull-down, pull-up these terms refer to resistors, sometimes internal to the device, which are permanently connected to either ground or v dd . pwm pulse width modulation. this term is used to describe a technique where the width of the high and low periods of a waveform is varied, usually to enable a representation of an analog value. qfp quad flat pack package. ram random access memory. fast read and wr ite, but contents are lost when the power is removed. rfi radio frequency interference. rti real-time interrupt. rom read-only memory. this type of memory is programmed during device manufacture and cannot subsequently be altered. rs-232c a standard serial communications protocol. sar successive approximation register. sci serial communications interface. set ?1? ? the logic one state; the opposite of ?clear?. silicon glen an area in the central belt of sc otland, so called because of the concentration of semiconductor manufacturers and users found there. single chip mode in this mode the device functions as a self contained unit, requiring only i/o devices to complete a system. spi serial peripheral interface. test mode this mode is intended for factory testing. ttl transistor-transistor logic. uart universal asynchronous receiver transmitter. vco voltage controlled oscillator. watchdog see ?cop?. wired-or a means of connecting outpu ts together such that the resulting composite output state is the logical or of the state of the individual outputs. word two bytes; 16 bits. xirq non-maskable interrupt request. the overline indicates that this has an active-low signal format. tpg 279
freescale iv mc68HC05B6 glossary this page left bl ank intentionally tpg 280
mc68HC05B6 freescale v index index in this index numeric entries are placed first; page references in italics indicate that the reference is to a figure. a a/d converter block diagram 8?2 during stop mode 8?6 during wait mode 8?6 operation 8?1 registers addata 8?3 adstat 8?4 portd 8?3 a/d converter characteristics 11?8 , 11?9 , e?24 , e?25 , f?22 , f?23 , h?25 , h?26 , i?3 a/d status/control register adon 4?5 absolute maximum ratings 11?1 addata ? a/d result data register 8?3 adon ? a/d converter on 8?5 adon ? a/d converter on bit 4?5 adrc ? a/d rc oscillator control 8?4 adstat adon 8?5 adrc 8?4 ch3-ch0 8?5 coco 8?4 adstat ? a/d status/control register 8?4 alternate counter register 5?3 analog input 8?6 b baud rate register scp1, scp0 6?18 scr2, scr1, scr0 6?19 sct2, sct1, sct0 6?18 block diagrams mc68hc05b16 d?3 mc68hc05b32 g?2 mc68hc05b4 a?2 mc68hc05b8 b?2 mc68hc705b16 e?2 mc68hc705b16n f?2 mc68hc705b32 h?4 mc68hc705b5 c?2 plm system 7?1 programmable timer 5?2 sci 6?2 , 6?2 watchdog system 9?3 bootstrap mode c?8 , e?10 , h?12 c ceramic resonator 2?11 ch3-ch0 ? a/d channels 3, 2, 1 and 0 8?5 coco ? conversion complete flag 8?4 control timing 11?10 , 11?11 , c?19 , e?26 , e?27 , f?24 , f?25 , h?27 , h?28 , i?4 cop watchdog 9?3 during stop mode 9?4 during wait mode 9?4 counter 5?1 counter register 5?3 cpha ? clock phase 6?12 cpol ? clock polarity 6?12 crystal 2?11 d data direction registers ddra, ddrb, ddrc 4?5 data format 6?5 dc electrical characteristics 11?2 , 11?5 , c?19 , e?22 , e?23 , f?20 , f?21 , h?23 , h?24 , i?2 e e1era ? eeprom erase/programming bit 3?3 , e?7 , f?7 , h?9 e1lat ? eeprom programming latch enable 3?4 e1lat ? eeprom programming latch enable bit e?7 , f?7 , h?10 281 282 283 284 285
freescale vi mc68HC05B6 index e1pgm ? eeprom charge pump enable/disable 3?4 , e?7 , f?7 , h?10 e6lat ? eprom programming latch enable bit e?6 , f?6 , h?9 e6pgm ? eprom program enable bit e?6 , f?6 , h?9 eclk ? external clock output bit 4?3 ee1p ? eeprom protect bit e?9 , f?9 ee1p ? eeprom protection bit h?12 eeprom 3?1 , 3?3 erase operation 3?5 programming operation 3?6 read operation 3?5 stop mode 3?7 wait mode 3?7 eeprom control register e1era 3?3 e1lat 3?4 e1pgm 3?4 eclk 3?3 eeprom options register ee1p e?9 , f?9 sec e?9, f?9 eeprom/eclk control eclk 4?3 elat ? eprom programming latch enable bit c?6 epgm ? eprom programming bit c?6 epp ? eprom protect c?7 eppt ? eprom protect test bit c?6 eprom 13?2 , c?5 , e?5 , f?5 control register c?6 , e?6 , f?6 options register c?7 program operation e?5 , f?6 , h?8 programming operation c?5 read operation e?5 , f?5 , h?8 eprom control register elat c?6 epgm c?6 eppt c?6 eprom electrical characteristics e?28 , f?26 , h?29 eprom registers c?6 eprom/eeprom/eclk control register e1era e?7 , f?7 e1lat e?7 , f?7 e1pgm e?7 , f?7 e6lat e?6 , f?6 e6pgm e?6 , f?6 external clock 2?12 , d?4 , e?5 , f?5 , g?2 external interrupt 9?7 f fe ? framing error flag 6?17 h high speed operation i?1 i i/o pin states 4?2 i/o port structure 4?2 , 4?2 icf1 ? input capture flag 1 5?6 icf2 ? input capture flag 2 5?7 idle ? idle line detect flag 6?16 iedg1 ? input edge 1 5?5 ilie ? idle line interrupt enable 6?14 input capture registers icr1 5?7 icr2 5?8 input/output programming 4?1 inte ? external interrupt enable 3?9 , 9?9 interrupts priorities 9?6 sci 9?10 swi 9?6 intp, intn ? external interrupt sensitivity options 3?9 , 9?9 irq 9?7 irq sensitivity 9?9 l lbcl ? last bit clock 6?13 low power modes slow 2?9 stop 2?6 wait 2?8 m m ? mode 6?11 mask option register pbpd e?8 , f?8 , h?11 pcpd e?8 , f?9 , h?11 rtim e?8 , f?8 , h?11 rwat e?8 , f?8 , h?11 wwat e?8 , f?8 , h?11 mask options mc68HC05B6 1?3 maskable hardware interrupts 9?7 maskset errata d?1 , h?1 mc68hc05b16 d?1 block diagram d?3 memory map d?5 mc68hc05b32 g?1 block diagram g?2 memory map g?3 mc68hc05b4 block diagram a?2 memory map a?3 mc68HC05B6 block diagram 1?3 mask options 1?3 memory map 3?2 pinouts 12?1 , 12?2 , 12?3 286
mc68HC05B6 freescale vii index mc68hc05b8 b?1 block diagram b?2 memory map b?3 mc68hc705b16 e?1 block diagram e?2 memory map e?3 mc68hc705b16n f?1 block diagram f?2 memory map f?3 mc68hc705b32 h?3 block diagram h?4 memory map h?5 mc68hc705b5 c?1 block diagram c?2 memory map c?3 mechanical dimensions 12?4 , 12?5 , 12?6 memory map mc68hc05b16 d?5 mc68hc05b32 g?3 mc68hc05b4 a?3 mc68HC05B6 3?2 mc68hc05b8 b?3 mc68hc705b16 e?3 mc68hc705b16n f?3 mc68hc705b32 h?5 mc68hc705b5 c?3 miscellaneous register inte 3?9 , 9?9 intp, intn 3?9 , 9?9 por 3?9 , 9?2 sfa 3?10 , 7?3 sfb 3?10 , 7?3 sm 2?9 , 3?10 , 7?3 wdog 3?10 , 9?4 modes of operation jump to any address 2?4 low power modes 2?6 single chip mode 2?1 n nf ? noise error flag 6?17 nonmaskable software interrupt 9?6 o ocf1 ? output compare flag 2 5?6 ocf2 ? output compare flag 2 5?7 ocie ? output compares interrupt enable 5?4 olv1 ? output level 1 5?5 olv2 ? output level 2 5?5 options register sec h?12 options register ee1p h?12 epp c?7 pbpd c?8 pcpd c?8 rtim c?7 rwat c?7 wwat c?7 optr ? options register 3?6 , c?7 ee1p ? eeprom protection bit 3?7 sec ? security bit 3?7 or ? overrun error flag 6?17 oscillator connections 2?12 , d?4 output compare registers ocr1 5?9 ocr2 5?10 p parallel bootstrap e?13 , e?19 , f?13 , h?16 pbpd ? port b pull-down e?8 , f?8 pbpd ? port b pull-down resistors c?8 pcpd ? port c pull-down e?8 , f?9 pcpd ? port c pull-down resistors c?8 pin configurations 12?1 pins irq 2?10 osc1, osc2 2?11 pa0?pa7, pb0?pb7, pc0?pc7 2?13 pd0/an0?pd7/an7 2?13 plma, plmb 2?13 rdi, tdo 2?13 reset 2?10 , 9?3 sclk 2?13 tcap1 2?10 tcap2 2?11 tcmp1, tcmp2 2?11 vdd, vss 2?10 vpp1 2?13 vrh, vrl 2?13 plcc 12?1 plm 5?11 block diagram 7?1 clock selection 7?4 plma, plmb 7?2 por ? power-on reset bit 3?9 , 9?2 port registers porta, portb 4?4 portc 4?4 portd 4?5 portd ? port d data register 8?3 ports a and b 4?2 c 4?3 d 4?3 power-on reset 9?2 programmable timer block diagram 5?2 pulse 5?11 pulse length modulation 5?11 registers plma, plmb 5?11
freescale viii mc68HC05B6 index pulse length modulation registers plma, plmb 5?11 q qfp 12?2 r r8 ? receive data bit 8 6?11 ram 3?1 rdi 6?6 rdrf ? receive data register full flag 6?16 re ? receiver enable 6?15 receive data in 6?6 receiver 6?3 register outline 3?8 registers 3?1 reset 9?3, e?5, f?5 reset timing diagram 9?1 resets 9?1 rie ? receiver interrupt enable 6?14 rom 3?1 rtim ? reset time c?7 , e?8 , f?8 rvu 13?2 rwat ? watchdog after reset c?7 , e?8 , f?8 rwu ? receiver wake-up 6?15 s sbk ? send break 6?15 sci block diagram 6?2 receiver 6?3 sampling technique 6?7 synchronous transmission 6?9 transmitter 6?3 two-wire system 6?1 sci interrupts 9?10 sci registers baud 6?18 sccr1 6?10 sccr2 6?14 scdr 6?10 scsr 6?16 scp1, scp0 ? serial prescaler select bits 6?18 scr2, scr1, scr0 ? sci rate select bits 6?19 sct2, sct1, sct0 ? sci rate select bits 6?18 sdip 12?3 sec ? secure bit e?9 , f?9 , h?12 self-check mode a?5 self-check rom 3?2 serial bootstrap e?16 serial communications control register 1 6?10 cpha 6?12 cpol 6?12 lbcl 6?13 m 6?11 r8 6?11 t8 6?11 wake 6?11 serial communications control register 2 ilie 6?14 re 6?15 rie 6?14 rwu 6?15 sbk 6?15 tcie 6?14 te 6?14 tie 6?14 serial communications data register 6?10 serial communications status register fe 6?17 idle 6?16 nf 6?17 or 6?17 rdrf 6?16 tc 6?16 tdre 6?16 serial ram loader 2?2 , f?16 , h?19 sfa ? slow or fast mode selection for plma 3?10 , 7?3 sfb ? slow or fast mode selection for plmb 3?10 , 7?3 single chip mode 2?1 slow 2?9 sm ? slow mode 3?10 , 7?3 sm ? slow mode selection bit 2?9 start bit detection 6?6 stop 2?6 , 3?7 , 5?12 , 6?21 , 7?4 , 8?6 , 9?4 t t8 ? transmit data bit 8 6?11 tc ? transmit complete flag 6?16 tcie ? transmit complete interrupt enable 6?14 tdo 6?8 tdre ? transmit data register empty flag 6?16 te ? transmitter enable 6?14 tie ? transmit interrupt enable 6?14 timer control register iedg1 5?5 ocie 5?4 olv1 5?5 olv2 5?5 toie 5?4 timer interrupts 9?10 timer state diagrams 5?12 timer status register icf1 5?6 icf2 5?7 ocf1 5?6 ocf2 5?7 tof 5?6 tof ? timer overflow status flag 5?6 toie ? timer overflow interrupt enable 5?4 transmit data out 6?8
mc68HC05B6 freescale ix index transmitter 6?3 tsr ? timer status register 5?6 v verification media 13?2 w wait 2?8 , 3?7 , 5?12 , 6?21 , 7?4 , 8?6 , 9?4 wake ? wake-up mode select 6?11 wake-up address mark 6?6 idle line 6?6 receiver 6?5 wdog ? watchdog enable/disable 3?10 , 9?4 wwat ? watchdog during wait mode c?7 , e?8 , f?8
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13. currently there is some discussion in the semiconductor indu stry regarding a move towards providing data sheets in electron ic form. if you have any opinion on this subject, please comment. 14. we would be grateful if you would supply the following information (at your discretion), or attach your card. name: phone no: position: fax no: department: company: address: thank you for helping us improve our documentation, graham forbes, technical publications manager, motorola ltd., scotland . ? cut along this line to remove ? ? third fold back along this line ? 8. how could we improve this document? 9. how would you rate motorola?s documentation? excellent poor ? in general ???? ? against other semiconductor suppliers ???? 10. which semiconductor manufacturer provides the best technical documentation? 11. which company (in any field) provides the best technical documentation? 12. how many years have you worked with microprocessors? less than 1 year ? 1?3 years ? 3?5 years ? more than 5 years ? ? second fold back along this line ? ? finally, tuck this edge into opposite flap ? ? by air mail par avion ne pas affranchir ibrs number phq-b/207/g ccri numero phq-b/207/g reponse payee grande-bretagne motorola ltd., colvilles road, kelvin industrial estate, east kilbride, g75 8br. great britain. f.a.o. technical publications manager (re: mc68HC05B6/d rev. 4) no stamp required ? first fold back along this line ? semiconductor products sector tpg 288
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 introduction modes of operation and pin descriptions memory and registers input/output ports programmable timer serial communications interface pulse length d/a converters analog to digital converter resets and interrupts cpu core and in struction set electrical specifications mechanical data ordering information appendices high speed operation tpg 289
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 introduction modes of operation and pin descriptions memory and registers input/output ports programmable timer serial communications interface pulse length d/a converters analog to digi tal converter resets and interrupts cpu core and instruction set electrical specifications mechanical data ordering information appendices high speed operation tpg 290

how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the arm powered logo is a registered trademark of arm limited. arm7tdmi-s is a trademark of arm limited. java and all other java-based marks are trademarks or registered trademarks of sun microsystems, inc. in the u.s. and other countries. the bluetooth trademarks are owned by their proprietor and used by freescale semiconductor, inc. under license. ? freescale semiconductor, inc. 2005. all rights reserved. rev. 4.1 mc68HC05B6/d 08/2005

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